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<td>The WBP mux module in <code>wr_core</code> randomly drops the status register of frames outputted from the core. Investigate and fix.</td>
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<td>Greg</td>
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<tr class="odd">
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<td>WR Core V2 interconnect</td>
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<td>Now Wesley's crossbar is fully operational - replace the intercon & LM32 CPU with the new components, using Pipelined Wishbone. Preserve one interconnect port of the intercon (accessible from outside the WR Core) for optional JTAG-over-Wishbone.</td>
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<td>Greg</td>
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<tr class="even">
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<td>WR Core mini-NIC RX DMA memory corruption</td>
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<td>The Minic sometimes goes out of the DMA RX buffer area designeted in RX_ADDR and RX_AVAIL registers, causing random crashes of the core. This has been temporarily fixed by adding MPROT registerm but must be properly investigated and fixed sometime.</td>
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<td>Greg</td>
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</tbody>
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</table>
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