The repository contains only generic and reusable White Rabbit cores, which should not be tied to any particular piece of hardware. If there are any platform dependencies, the platform-specific part should be clearly separated from the generic part.
The repo is organized as follows:
-`modules` - "big" modules, such as the WR Endpoint of WR Core - each
in a separate subdirectory, with dir name matching the name of of
the top level entity. Only platform-independent RTL code is allowed.
-`platform` - platform dependent code, for example wrappers for
gigabit transceivers or Chipscope cores.
-`sim` - simulation models and header files
-`top` - top level entities for actual hardware implementations (i.e.
FPGA-wide top levels). Each design should be placed in a separate
subdirectory with the name matching the pattern
`hw_platform`/@firmware\_name`. For example,
`spec\_1\_1/wr\_core\_demo@ means a demo project for the WR core
synthesized for the SPEC 1.1. card. FPGA pin assignment files should
be also stored in top/ subdirectory.
## Coding style:
In general, the OHR VHDL coding guidelines should be followed. However,
In general, the OHR VHDL coding guidelines should be followed. However,
due to large complexity of some of the modules, there are some
due to large complexity of some of the modules, there are some