| ... | ... | @@ -81,6 +81,437 @@ There are five generics provided for the parametrisation of the module. |
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#### Module Ports
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The following table lists all the input/output ports of the module. Note
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that depending on the values of the module generics (`g_fabric_iface` in
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particular), not all ports are required.
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<table>
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<tbody>
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<tr class="odd">
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<td align="center"><strong>name</strong></td>
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<td><strong>direction</strong></td>
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<td><strong>type</strong></td>
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<td><strong>description</strong></td>
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</tr>
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<tr class="even">
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<td align="center"><strong>Clocks/resets</strong></td>
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</tr>
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<tr class="odd">
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<td align="center">clk_board_125m_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>-- Clock inputs from the board</td>
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</tr>
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<tr class="even">
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<td align="center">clk_board_20m_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>-- Clock inputs from the board</td>
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</tr>
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<tr class="odd">
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<td align="center">areset_n_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>-- Reset input (active low, can be async)</td>
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</tr>
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<tr class="even">
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<td align="center">clk_sys_62m5_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>-- 62.5MHz sys clock output</td>
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</tr>
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<tr class="odd">
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<td align="center">clk_ref_125m_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>-- 125MHz ref clock output</td>
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</tr>
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<tr class="even">
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<td align="center">rst_sys_62m5_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>-- active high reset output, synchronous to clk_sys_62m5_o</td>
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</tr>
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<tr class="odd">
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<td align="center"><strong>SPI interfaces to DACs</strong></td>
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</tr>
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<tr class="even">
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<td align="center">dac_ref_sync_n_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">dac_dmtd_sync_n_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center">dac_din_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">dac_sclk_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center"><strong>SFP I/O for transceiver and SFP management info from VFC-HD</strong></td>
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</tr>
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<tr class="odd">
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<td align="center">sfp_tx_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center">sfp_rx_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">sfp_det_valid_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>-- HIGH if both of the following are true: -- 1. SFP is detected (plugged in) -- 2. The part number has been successfully read after the SFP detection</td>
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</tr>
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<tr class="even">
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<td align="center">sfp_data_i</td>
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<td>in</td>
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<td>std_logic_vector (127 downto 0)</td>
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<td>-- 16 byte vendor Part Number (PN) -- (ASCII encoded, first character byte in bits 127 downto 120)</td>
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</tr>
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<tr class="odd">
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<td align="center"><strong>I2C EEPROM</strong></td>
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</tr>
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<tr class="even">
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<td align="center">eeprom_sda_b</td>
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<td>inout</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">eeprom_scl_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>-- VFC-HD defines SCL as output, which works because the EEPROM is the -- only device connected on this I2C bus.</td>
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</tr>
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<tr class="even">
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<td align="center"><strong>Onewire interface</strong></td>
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</tr>
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<tr class="odd">
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<td align="center">onewire_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center">onewire_oen_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center"><strong>External WB interface</strong></td>
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</tr>
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<tr class="even">
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<td align="center">wb_adr_i</td>
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<td>in</td>
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<td>std_logic_vector</td>
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<td>WR fabric "sink" interface. VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD)</td>
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</tr>
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<tr class="odd">
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<td align="center">wb_dat_i</td>
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<td>in</td>
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<td>std_logic_vector</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center">wb_dat_o</td>
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<td>out</td>
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<td>std_logic_vector</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">wb_sel_i</td>
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<td>in</td>
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<td>std_logic_vector</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center">wb_we_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">wb_cyc_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center">wb_stb_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">wb_ack_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center">wb_int_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">wb_err_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center">wb_rty_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">wb_stall_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center"><strong>WR fabric interface <em><span class=""plain"@ = @g_fabric_iface when used only"></span></em></strong></td>
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</tr>
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<tr class="odd">
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<td align="center">wrf_src_adr_o</td>
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<td>out</td>
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<td>std_logic_vector</td>
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<td>Pipelined Wishbone master interface. It passes all the Ethernet frames received from a physical link to a slave interface implemented in a user-defined module.<br />
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VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD).</td>
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</tr>
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<tr class="even">
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<td align="center">wrf_src_dat_o</td>
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<td>out</td>
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<td>std_logic_vector</td>
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</tr>
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<tr class="odd">
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<td align="center">wrf_src_cyc_o</td>
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<td>out</td>
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<td>std_logic</td>
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</tr>
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<tr class="even">
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<td align="center">wrf_src_stb_o</td>
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<td>out</td>
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<td>std_logic</td>
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</tr>
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<tr class="odd">
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<td align="center">wrf_src_we_o</td>
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<td>out</td>
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<td>std_logic</td>
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</tr>
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<tr class="even">
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<td align="center">wrf_src_sel_o</td>
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<td>out</td>
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<td>std_logic_vector</td>
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</tr>
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<tr class="odd">
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<td align="center">wrf_src_ack_i</td>
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<td>in</td>
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<td>std_logic</td>
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</tr>
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<tr class="even">
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<td align="center">wrf_src_stall_i</td>
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<td>in</td>
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<td>std_logic</td>
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</tr>
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<tr class="odd">
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<td align="center">wrf_src_err_i</td>
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<td>in</td>
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<td>std_logic</td>
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</tr>
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<tr class="even">
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<td align="center">wrf_src_rty_i</td>
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<td>in</td>
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<td>std_logic</td>
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</tr>
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<tr class="odd">
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<td align="center">wrf_snk_adr_i</td>
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<td>in</td>
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<td>std_logic_vector</td>
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<td>Pipelined Wishbone slave interface. It receives Ethernet frames from a master interface implemented in a user-defined module, and sends them to a physical link.<br />
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VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD).</td>
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</tr>
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<tr class="even">
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<td align="center">wrf_snk_dat_i</td>
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<td>in</td>
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<td>std_logic_vector</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">wrf_snk_cyc_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center">wrf_snk_stb_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">wrf_snk_we_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center">wrf_snk_sel_i</td>
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<td>in</td>
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<td>std_logic_vector</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">wrf_snk_ack_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center">wrf_snk_stall_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">wrf_snk_err_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center">wrf_snk_rty_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center"><strong>WR streamers <em><span class=""streamers"@ = @g_fabric_iface when used only"></span></em></strong></td>
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</tr>
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<tr class="even">
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<td align="center">wrs_tx_data_i</td>
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<td>in</td>
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<td>std_logic_vector</td>
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<td>The width of the vector is equal to g_streamer_width parameter.</td>
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</tr>
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<tr class="odd">
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<td align="center">wrs_tx_valid_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="even">
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<td align="center">wrs_tx_dreq_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td align="center">wrs_tx_last_i</td>
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<td>in</td>
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|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrs_tx_flush_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrs_rx_first_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrs_rx_last_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrs_rx_data_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td>The width of the vector is equal to g_streamer_width parameter.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrs_rx_valid_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrs_rx_dreq_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center"><strong>WRPC timing interface and status</strong></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">pps_p_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>1-PPS (Pulse Per Second) signal generated in the clk_ref_125m_o clock domain and aligned to WR time, pulse generated when the cycle counter is 0 (beginning of each full TAI second).</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">tm_time_valid_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>If 1, the timecode generated by the WRPC is valid.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">tm_tai_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td>TAI part of the timecode (40 bits).</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">tm_cycles_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td>Fractional part of each second represented by the state of counter clocked with the frequency 125 MHz (values from 0 to 124999999, each count is 8 ns).</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">led_link_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>signal for driving Ethernet Link LED.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">led_act_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>signal for driving Ethernet Act LED.</td>
|
|
|
|
</tr>
|
|
|
|
</tbody>
|
|
|
|
</table>
|
|
|
|
|
|
|
|
## Software for the embedded CPU of the WR PTP core
|
|
|
|
|
|
|
|
The WR PTP core also instantiates an embedded softcore CPU (LM32), which
|
| ... | ... | |
