| ... | ... | @@ -7,6 +7,12 @@ project](https://www.ohwr.org/project/wr-cores/wikis) provides support |
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for the [VFC-HD board](https://www.ohwr.org/project/vfc-hd/wikis), an
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FMC carrier board based on an Arria V FPGA from Altera.
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## Gateware
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The main ingredient of the WR PTP core is the FPGA gateware. The WR PTP
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core in the form of a parametrisable VHDL module, to be instantiated in
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your own design.
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By using this module, the user gains the benefit of instantiating all
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the necessary components of the WR PTP core (including the core itself,
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the PHY, PLLs, etc.) in one go, without having to delve into the
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| ... | ... | @@ -19,12 +25,6 @@ suggested to use this code as a reference, and to consider using the |
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internally in this module) for instantiating the PHY and (optionally)
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the PLLs.
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## Gateware
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The main ingredient of the WR PTP core is the FPGA gateware. The WR PTP
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core in the form of a parametrisable VHDL module, to be instantiated in
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your own design.
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### Getting it
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The FPGA gateware is available on the
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| ... | ... | @@ -46,467 +46,12 @@ project, is located under |
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A VHDL package with the definition of the module can be found under
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[board/wr\_board\_pkg.vhd](https://www.ohwr.org/project/wr-cores/tree/dlamprid-vfchd/).
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#### Module Generics
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There are five generics provided for the parametrisation of the module.
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>name</strong></td>
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<td><strong>type</strong></td>
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<td><strong>default</strong></td>
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<td><strong>description</strong></td>
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</tr>
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<tr class="even">
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<td>g_simulation</td>
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<td>integer</td>
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<td>0</td>
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<td>This can be set to 1 to enable faster simulation, by speeding up some of the initialisation processes.</td>
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</tr>
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<tr class="odd">
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<td>g_pcs16_bit</td>
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<td>boolean</td>
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<td>false</td>
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<td>The VFC-HD makes use of the <a href="platform-arria5">Altera Arria V platform</a> for WhiteRabbit, which provides the possibility to configure the PCS of the PHY either as 8bit or 16bit. The default is to use the 8bit PCS, but this generic can be used to override it.</td>
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</tr>
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<tr class="even">
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<td>g_fabric_iface</td>
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<td>string</td>
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<td>"plain"</td>
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<td>The WR PTP core provides a [fabric" interface towards the FPGA. The default value for this generic will leave the fabric interface as is. If instead it is set to "streamers", a <a href="WR-Streamers">WhiteRabbit streamer</a> module will be attached to it. In the future, it is foreseen to have a third option here, for instantiating an "Etherbone core](https://www.ohwr.org/project/etherbone-core/wikis).</td>
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</tr>
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<tr class="odd">
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<td>g_streamer_width</td>
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<td>integer</td>
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<td>32</td>
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<td>In case <code>g_fabric_iface = "streamers"</code>, then this generic defines the data width for the streamer interface. Otherwise, it is ignored.</td>
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</tr>
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<tr class="even">
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<td>g_dpram_initf</td>
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<td>string</td>
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<td>"default"</td>
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<td>This generic can point to the path of the Altera memory initialisation file (.mif) containing the software binary for the embedded CPU of the WR PTP core. If provided, it will be included in the final FPGA bitstream and the embedded CPU will be properly initialised every time the FPGA is programmed with the bitstream.</td>
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</tr>
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</tbody>
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</table>
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#### Module Ports
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The following table lists all the input/output ports of the module. Note
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that depending on the values of the module generics (`g_fabric_iface` in
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particular), not all ports are required.
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<table>
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<tbody>
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<tr class="odd">
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<td align="center"><strong>name</strong></td>
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<td><strong>direction</strong></td>
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<td><strong>type</strong></td>
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<td><strong>description</strong></td>
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</tr>
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<tr class="even">
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<td align="center"><strong>Clocks/resets</strong></td>
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</tr>
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<tr class="odd">
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<td align="center">clk_board_125m_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>125 MHz clock input from the VFC-HD board (OSC2 output on the board).</td>
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</tr>
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<tr class="even">
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<td align="center">clk_board_20m_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>20 MHz clock input from the VFC-HD board (OSC3 output on the board).</td>
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</tr>
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<tr class="odd">
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<td align="center">areset_n_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>Reset input, active low. Can be asynchronous.</td>
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</tr>
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<tr class="even">
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<td align="center">clk_sys_62m5_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>62.5MHz system clock output.</td>
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</tr>
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<tr class="odd">
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<td align="center">clk_ref_125m_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>125MHz WR reference clock output.</td>
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</tr>
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<tr class="even">
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<td align="center">rst_sys_62m5_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>Active high reset output, synchronous to clk_sys_62m5_o.</td>
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</tr>
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<tr class="odd">
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<td align="center"><strong>SPI interfaces to DACs</strong></td>
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</tr>
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<tr class="even">
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<td align="center">dac_ref_sync_n_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>SPI CSn for main (ref) VCXO</td>
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</tr>
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<tr class="odd">
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<td align="center">dac_dmtd_sync_n_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>SPI CSn for helper (DMTD) VCXO</td>
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</tr>
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<tr class="even">
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<td align="center">dac_din_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>SPI MOSI</td>
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</tr>
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<tr class="odd">
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<td align="center">dac_sclk_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>SPI CLK</td>
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</tr>
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<tr class="even">
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<td align="center"><strong>SFP I/O for transceiver and SFP management info from VFC-HD</strong></td>
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</tr>
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<tr class="odd">
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<td align="center">sfp_tx_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>SFP TX</td>
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</tr>
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<tr class="even">
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<td align="center">sfp_rx_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>SFP RX</td>
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</tr>
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<tr class="odd">
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<td align="center">sfp_det_valid_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td><em>High</em> if both of the following are true:<br />
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1. SFP is detected (plugged in)<br />
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2. The part number has been successfully read after the SFP detection</td>
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</tr>
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<tr class="even">
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<td align="center">sfp_data_i</td>
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<td>in</td>
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<td>std_logic_vector</td>
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|
<td>The VFC-HD board implements I2C multiplexers to provide access to the numerous SFP interfaces (as well as other I2C-controlled peripherals).<br />
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|
The <a href="https://gitlab.cern.ch/dlamprid/VFC-HD/tree/master">VFC-HD project</a> provides an additional module (in Verilog) which takes care of accessing the SFP information and making it available to the WR PTP code, in the form of a 16 byte vendor Part Number (128 bits std_logic_vector, ASCII encoded, first character byte in bits 127 downto 120).</td>
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</tr>
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<tr class="odd">
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<td align="center"><strong>I2C EEPROM</strong></td>
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</tr>
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<tr class="even">
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<td align="center">eeprom_sda_b</td>
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<td>inout</td>
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<td>std_logic</td>
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<td>Bidirectional I2C SDA line.</td>
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</tr>
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<tr class="odd">
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<td align="center">eeprom_scl_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>Normally, this should also be bidirectional, but VFC-HD defines SCL as output, which works because the EEPROM is the only device connected on this I2C bus.</td>
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</tr>
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<tr class="even">
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<td align="center"><strong>Onewire interface</strong></td>
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</tr>
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<tr class="odd">
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<td align="center">onewire_i</td>
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<td>in</td>
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<td>std_logic</td>
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|
<td>Data input from the onewire interface.</td>
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</tr>
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|
<tr class="even">
|
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|
|
<td align="center">onewire_oen_o</td>
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<td>out</td>
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<td>std_logic</td>
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|
<td>Output enable to the onewire interface. When this is asserted, the instantiating module should drive the onewire data output to ground.</td>
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</tr>
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|
<tr class="odd">
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<td align="center"><strong>External WB interface</strong></td>
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</tr>
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<tr class="even">
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|
<td align="center">wb_adr_i</td>
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<td>in</td>
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<td>std_logic_vector</td>
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|
<td>Wishbone slave interface, operating in "Pipelined" mode, with word granularity. It provides access to all the Wishbone peripherals inside the WR PTP core.<br />
|
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|
|
VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD).</td>
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</tr>
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<tr class="odd">
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|
<td align="center">wb_dat_i</td>
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<td>in</td>
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<td>std_logic_vector</td>
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</tr>
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<tr class="even">
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|
<td align="center">wb_dat_o</td>
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<td>out</td>
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<td>std_logic_vector</td>
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</tr>
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|
<tr class="odd">
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|
<td align="center">wb_sel_i</td>
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<td>in</td>
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|
<td>std_logic_vector</td>
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|
</tr>
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|
<tr class="even">
|
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|
<td align="center">wb_we_i</td>
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<td>in</td>
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<td>std_logic</td>
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</tr>
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|
<tr class="odd">
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|
<td align="center">wb_cyc_i</td>
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<td>in</td>
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<td>std_logic</td>
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</tr>
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<tr class="even">
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|
<td align="center">wb_stb_i</td>
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<td>in</td>
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|
<td>std_logic</td>
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|
</tr>
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|
<tr class="odd">
|
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|
<td align="center">wb_ack_o</td>
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<td>out</td>
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<td>std_logic</td>
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</tr>
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|
<tr class="even">
|
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|
<td align="center">wb_int_o</td>
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<td>out</td>
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|
<td>std_logic</td>
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|
</tr>
|
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|
<tr class="odd">
|
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|
<td align="center">wb_err_o</td>
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|
<td>out</td>
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|
<td>std_logic</td>
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|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wb_rty_o</td>
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|
|
<td>out</td>
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|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wb_stall_o</td>
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|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center"><strong>WR fabric interface <em><span class=""plain"@ = @g_fabric_iface when used only"></span></em></strong></td>
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|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_src_adr_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td>Pipelined Wishbone master interface. It passes all the Ethernet frames received from a physical link to a slave interface implemented in a user-defined module.<br />
|
|
|
|
VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD).</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_src_dat_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_src_cyc_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_src_stb_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_src_we_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_src_sel_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_src_ack_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_src_stall_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_src_err_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_src_rty_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_snk_adr_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td>Pipelined Wishbone slave interface. It receives Ethernet frames from a master interface implemented in a user-defined module, and sends them to a physical link.<br />
|
|
|
|
VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD).</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_snk_dat_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_snk_cyc_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_snk_stb_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_snk_we_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_snk_sel_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_snk_ack_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_snk_stall_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_snk_err_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_snk_rty_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center"><strong>WR streamers <em><span class=""streamers"@ = @g_fabric_iface when used only"></span></em></strong></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrs_tx_data_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td>Data word to be sent over the physical link. The width of the vector is equal to g_streamer_width parameter.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrs_tx_valid_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>An '1' indicates that the tx_data_i contains a valid data word.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrs_tx_dreq_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>Synchronous data request: when '1', the user may send a data word in the following clock cycle.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrs_tx_last_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>An '1' indicates the last data word in a larger block of samples.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrs_tx_flush_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>When asserted, the streamer will immediately send out all the data that is stored in its TX buffer.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrs_rx_first_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>An '1' indicates the first data word of the data block on wrs_rx_data_o.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrs_rx_last_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>An '1' indicates the last data word of the data block on wrs_rx_data_o.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrs_rx_data_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td>Data word received from the physical link. The width of the vector is equal to g_streamer_width parameter.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrs_rx_valid_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>An '1' indicates that rx_data_o is outputting a valid data word.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrs_rx_dreq_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>Synchronous data request input: when '1', the streamer may output another data word in the subsequent clock cycle.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center"><strong>WRPC timing interface and status</strong></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">pps_p_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>1-PPS (Pulse Per Second) signal generated in the clk_ref_125m_o clock domain and aligned to WR time, pulse generated when the cycle counter is 0 (beginning of each full TAI second).</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">tm_time_valid_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>If 1, the timecode generated by the WRPC is valid.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">tm_tai_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td>TAI part of the timecode (40 bits).</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">tm_cycles_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td>Fractional part of each second represented by the state of counter clocked with the frequency 125 MHz (values from 0 to 124999999, each count is 8 ns).</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">led_link_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>signal for driving Ethernet Link LED.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">led_act_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td>signal for driving Ethernet Act LED.</td>
|
|
|
|
</tr>
|
|
|
|
</tbody>
|
|
|
|
</table>
|
|
|
|
A [detailed description of all generics and ports](Board-vfc-hd-ports)
|
|
|
|
is also provided.
|
|
|
|
|
|
|
|
An example (Verilog) instantiation of this module can be found in the
|
|
|
|
[VFC-HD base
|
|
|
|
project](https://gitlab.cern.ch/dlamprid/VFC-HD/blob/master/Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v).
|
|
|
|
|
|
|
|
## Software for the embedded CPU of the WR PTP core
|
|
|
|
|
| ... | ... | @@ -626,5 +171,5 @@ wiki](https://www.ohwr.org/project/vfc-hd/wikis). |
|
|
|
|
|
|
|
-----
|
|
|
|
|
|
|
|
19 December 2016
|
|
|
|
20 December 2016
|
|
|
|
|
