| ... | ... | @@ -100,37 +100,37 @@ particular), not all ports are required. |
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<td align="center">clk_board_125m_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>-- Clock inputs from the board</td>
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<td>125 MHz clock input from the VFC-HD board (OSC2 output).</td>
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</tr>
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<tr class="even">
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<td align="center">clk_board_20m_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>-- Clock inputs from the board</td>
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<td>20 MHz clock input from the VFC-HD board (OSC3 output).</td>
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</tr>
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<tr class="odd">
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<td align="center">areset_n_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>-- Reset input (active low, can be async)</td>
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<td>Reset input, active low. Can be asynchronous.)</td>
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</tr>
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<tr class="even">
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<td align="center">clk_sys_62m5_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>-- 62.5MHz sys clock output</td>
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<td>62.5MHz system clock output.</td>
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</tr>
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<tr class="odd">
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<td align="center">clk_ref_125m_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>-- 125MHz ref clock output</td>
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<td>125MHz WR reference clock output.</td>
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</tr>
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<tr class="even">
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<td align="center">rst_sys_62m5_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td>-- active high reset output, synchronous to clk_sys_62m5_o</td>
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<td>Active high reset output, synchronous to clk_sys_62m5_o.</td>
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</tr>
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<tr class="odd">
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<td align="center"><strong>SPI interfaces to DACs</strong></td>
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| ... | ... | @@ -139,25 +139,25 @@ particular), not all ports are required. |
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<td align="center">dac_ref_sync_n_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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<td>SPI CSn for main (ref) VCXO</td>
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</tr>
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<tr class="odd">
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<td align="center">dac_dmtd_sync_n_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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<td>SPI CSn for helper (DMTD) VCXO</td>
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</tr>
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<tr class="even">
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<td align="center">dac_din_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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<td>SPI MOSI</td>
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</tr>
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<tr class="odd">
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<td align="center">dac_sclk_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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<td>SPI CLK</td>
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</tr>
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<tr class="even">
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<td align="center"><strong>SFP I/O for transceiver and SFP management info from VFC-HD</strong></td>
|
| ... | ... | @@ -166,25 +166,28 @@ particular), not all ports are required. |
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<td align="center">sfp_tx_o</td>
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<td>out</td>
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<td>std_logic</td>
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<td></td>
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<td>SFP TX</td>
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</tr>
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<tr class="even">
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<td align="center">sfp_rx_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td></td>
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<td>SFP RX</td>
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</tr>
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<tr class="odd">
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<td align="center">sfp_det_valid_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>-- HIGH if both of the following are true: -- 1. SFP is detected (plugged in) -- 2. The part number has been successfully read after the SFP detection</td>
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<td><em>High</em> if both of the following are true:<br />
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1. SFP is detected (plugged in)<br />
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2. The part number has been successfully read after the SFP detection</td>
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</tr>
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<tr class="even">
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|
<td align="center">sfp_data_i</td>
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<td>in</td>
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<td>std_logic_vector (127 downto 0)</td>
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<td>-- 16 byte vendor Part Number (PN) -- (ASCII encoded, first character byte in bits 127 downto 120)</td>
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<td>std_logic_vector</td>
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<td>The VFC-HD board implements I2C multiplexers to provide access to the numerous SFP interfaces (as well as other I2C-controlled peripherals).<br />
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The <a href="https://gitlab.cern.ch/dlamprid/VFC-HD/tree/master">VFC-HD project</a> provides an additional module (in Verilog) which takes care of accessing the SFP information and making it available to the WR PTP code, in the form of a 16 byte vendor Part Number (128 bits std_logic_vector, ASCII encoded, first character byte in bits 127 downto 120).</td>
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</tr>
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<tr class="odd">
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|
<td align="center"><strong>I2C EEPROM</strong></td>
|
| ... | ... | @@ -193,13 +196,13 @@ particular), not all ports are required. |
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<td align="center">eeprom_sda_b</td>
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<td>inout</td>
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<td>std_logic</td>
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<td></td>
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|
<td>Bidirectional I2C SDA line.</td>
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</tr>
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<tr class="odd">
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|
<td align="center">eeprom_scl_o</td>
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<td>out</td>
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|
<td>std_logic</td>
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<td>-- VFC-HD defines SCL as output, which works because the EEPROM is the -- only device connected on this I2C bus.</td>
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|
<td>Normally, this should also be bidirectional, but VFC-HD defines SCL as output, which works because the EEPROM is the only device connected on this I2C bus.</td>
|
|
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|
</tr>
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|
|
<tr class="even">
|
|
|
|
<td align="center"><strong>Onewire interface</strong></td>
|
| ... | ... | @@ -208,13 +211,13 @@ particular), not all ports are required. |
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|
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<td align="center">onewire_i</td>
|
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|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
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|
|
|
<td></td>
|
|
|
|
<td>Data input from the onewire interface.</td>
|
|
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</tr>
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|
<tr class="even">
|
|
|
|
<td align="center">onewire_oen_o</td>
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|
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<td>out</td>
|
|
|
|
<td>std_logic</td>
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|
|
|
<td></td>
|
|
|
|
<td>Output enable to the onewire interface. When this is asserted, the instantiating module should drive the onewire data output to ground.</td>
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|
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|
</tr>
|
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|
|
<tr class="odd">
|
|
|
|
<td align="center"><strong>External WB interface</strong></td>
|
| ... | ... | @@ -223,7 +226,8 @@ particular), not all ports are required. |
|
|
|
<td align="center">wb_adr_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td>WR fabric "sink" interface. VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD)</td>
|
|
|
|
<td>Wishbone slave interface, operating in "Pipelined" mode, with word granularity. It provides access to all the Wishbone peripherals inside the WR PTP core.<br />
|
|
|
|
VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD).</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wb_dat_i</td>
|
| ... | ... | @@ -305,46 +309,55 @@ VHDL records are not used here, to facilitate integration of the module into Ver |
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|
|
<td align="center">wrf_src_dat_o</td>
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|
|
|
<td>out</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_src_cyc_o</td>
|
|
|
|
<td>out</td>
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|
|
|
<td>std_logic</td>
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|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_src_stb_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_src_we_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_src_sel_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_src_ack_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_src_stall_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_src_err_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrf_src_rty_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrf_snk_adr_i</td>
|
| ... | ... | @@ -414,61 +427,61 @@ VHDL records are not used here, to facilitate integration of the module into Ver |
|
|
|
<td align="center">wrs_tx_data_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td>The width of the vector is equal to g_streamer_width parameter.</td>
|
|
|
|
<td>Data word to be sent over the physical link. The width of the vector is equal to g_streamer_width parameter.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrs_tx_valid_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
<td>An '1' indicates that the tx_data_i contains a valid data word.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrs_tx_dreq_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
<td>Synchronous data request: when '1', the user may send a data word in the following clock cycle.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrs_tx_last_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
<td>An '1' indicates the last data word in a larger block of samples.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrs_tx_flush_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
<td>When asserted, the streamer will immediately send out all the data that is stored in its TX buffer.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrs_rx_first_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
<td>An '1' indicates the first data word of the data block on wrs_rx_data_o.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrs_rx_last_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
<td>An '1' indicates the last data word of the data block on wrs_rx_data_o.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrs_rx_data_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic_vector</td>
|
|
|
|
<td>The width of the vector is equal to g_streamer_width parameter.</td>
|
|
|
|
<td>Data word received from the physical link. The width of the vector is equal to g_streamer_width parameter.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center">wrs_rx_valid_o</td>
|
|
|
|
<td>out</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
<td>An '1' indicates that rx_data_o is outputting a valid data word.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td align="center">wrs_rx_dreq_i</td>
|
|
|
|
<td>in</td>
|
|
|
|
<td>std_logic</td>
|
|
|
|
<td></td>
|
|
|
|
<td>Synchronous data request input: when '1', the streamer may output another data word in the subsequent clock cycle.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td align="center"><strong>WRPC timing interface and status</strong></td>
|
| ... | ... | @@ -630,5 +643,5 @@ wiki](https://www.ohwr.org/project/vfc-hd/wikis). |
|
|
|
|
|
|
|
-----
|
|
|
|
|
|
|
|
16 December 2016
|
|
|
|
19 December 2016
|
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|
