... | ... | @@ -112,19 +112,19 @@ particular), not all ports are required. |
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<td align="center">clk_board_125m_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>125 MHz clock input from the VFC-HD board (OSC2 output).</td>
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<td>125 MHz clock input from the VFC-HD board (OSC2 output on the board).</td>
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</tr>
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<tr class="even">
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<td align="center">clk_board_20m_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>20 MHz clock input from the VFC-HD board (OSC3 output).</td>
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<td>20 MHz clock input from the VFC-HD board (OSC3 output on the board).</td>
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</tr>
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<tr class="odd">
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<td align="center">areset_n_i</td>
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<td>in</td>
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<td>std_logic</td>
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<td>Reset input, active low. Can be asynchronous.)</td>
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<td>Reset input, active low. Can be asynchronous.</td>
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</tr>
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<tr class="even">
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<td align="center">clk_sys_62m5_o</td>
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