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Provided description for module generics and links to VHDL code authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Board-vfc-hd.md
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......@@ -28,12 +28,65 @@ To get it,
### Using it
### Software for the embedded CPU of the WR PTP core
The top-level VHDL module, which you can include in your own VFC-HD
project, is located under
[board/vfchd/xwrc\_board\_vfchd.vhd](https://www.ohwr.org/project/wr-cores/tree/dlamprid-vfchd/).
A VHDL package with the definition of the module can be found under
[board/wr\_board\_pkg.vhd](https://www.ohwr.org/project/wr-cores/tree/dlamprid-vfchd/).
#### Module Generics
There are five generics provided for the parametrisation of the module.
<table>
<tbody>
<tr class="odd">
<td><strong>name</strong></td>
<td><strong>type</strong></td>
<td><strong>default</strong></td>
<td><strong>description</strong></td>
</tr>
<tr class="even">
<td>g_simulation</td>
<td>integer</td>
<td>0</td>
<td>This can be set to 1 to enable faster simulation, by speeding up some of the initialisation processes.</td>
</tr>
<tr class="odd">
<td>g_pcs16_bit</td>
<td>boolean</td>
<td>false</td>
<td>The VFC-HD makes use of the <a href="platform-arria5">Altera Arria V platform</a> for WhiteRabbit, which provides the possibility to configure the PCS of the PHY either as 8bit or 16bit. The default is to use the 8bit PCS, but this generic can be used to override it.</td>
</tr>
<tr class="even">
<td>g_fabric_iface</td>
<td>string</td>
<td>&quot;plain&quot;</td>
<td>The WR PTP core provides a [fabric&quot; interface towards the FPGA. The default value for this generic will leave the fabric interface as is. If instead it is set to &quot;streamers&quot;, a WhiteRabbit streamer module will be attached to it. In the future, it is foreseen to have a third option here, for instantiating an &quot;Etherbone core](https://www.ohwr.org/project/etherbone-core/wikis).</td>
</tr>
<tr class="odd">
<td>g_streamer_width</td>
<td>integer</td>
<td>32</td>
<td>In case <code>g_fabric_iface = &quot;streamers&quot;</code>, then this generic defines the data width for the streamer interface. Otherwise, it is ignored.</td>
</tr>
<tr class="even">
<td>g_dpram_initf</td>
<td>string</td>
<td>&quot;default&quot;</td>
<td>This generic can point to the path of the Altera memory initialisation file (.mif) containing the software binary for the embedded CPU of the WR PTP core. If provided, it will be included in the final FPGA bitstream and the embedded CPU will be properly initialised every time the FPGA is programmed with the bitstream.</td>
</tr>
</tbody>
</table>
#### Module Ports
## Software for the embedded CPU of the WR PTP core
The WR PTP core also instantiates an embedded softcore CPU (LM32), which
requires its own software for proper operation.
#### Getting it
### Getting it
The embedded software for the WR PTP core is available on the
[eeprom\_scan](https://www.ohwr.org/project/wrpc-sw/tree/eeprom_scan/)
......@@ -46,7 +99,7 @@ To get it,
git clone -b eeprom_scan git:https://www.ohwr.org/hdl-core-lib/wr-cores/wrpc-sw.git
cd wrpc-sw; git submodule update --init
#### Using it
### Using it
Building and running the embedded software is described in the [White
Rabbit PTP Core User's Manual](/Current-release#documentation).
......@@ -59,7 +112,7 @@ interface (CONFIG\_AUX\_DIAG option).
The resulting binary can be either added to your HDL design (see TODO),
or injected to the CPU during runtime (see TODO).
## Software tools provided
## Software tools
Several software tools are provided, to facilitate the programming and
monitoring of the WR PTP core on the VFC-HD.
......