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for the [VFC-HD board](https://www.ohwr.org/project/vfc-hd/wikis), an
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FMC carrier board based on an Arria V FPGA from Altera.
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By using this module, the user gains the benefit of instantiating all
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the necessary components of the WR PTP core (including the core itself,
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the PHY, PLLs, etc.) in one go, without having to delve into the
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implementation details, using a setup that has been tested and is known
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to work well on the VFC-HD board.
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For users who need more control and flexibility over the process, it is
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suggested to use this code as a reference, and to consider using the
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[Altera Arria V platform](platform-arria5) (which is also used
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internally in this module) for instantiating the PHY and (optionally)
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the PLLs.
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## Gateware
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The main ingredient of the WR PTP core is the FPGA gateware. The WR PTP
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