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Board vfc hd · Changes

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removed extra empty column from data ports table authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Board-vfc-hd.md
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......@@ -245,67 +245,56 @@ VHDL records are not used here, to facilitate integration of the module into Ver
<td align="center">wb_dat_i</td>
<td>in</td>
<td>std_logic_vector</td>
<td></td>
</tr>
<tr class="even">
<td align="center">wb_dat_o</td>
<td>out</td>
<td>std_logic_vector</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wb_sel_i</td>
<td>in</td>
<td>std_logic_vector</td>
<td></td>
</tr>
<tr class="even">
<td align="center">wb_we_i</td>
<td>in</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wb_cyc_i</td>
<td>in</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="even">
<td align="center">wb_stb_i</td>
<td>in</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wb_ack_o</td>
<td>out</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="even">
<td align="center">wb_int_o</td>
<td>out</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wb_err_o</td>
<td>out</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="even">
<td align="center">wb_rty_o</td>
<td>out</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wb_stall_o</td>
<td>out</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="even">
<td align="center"><strong>WR fabric interface <em><span class="&quot;plain&quot;@ = @g_fabric_iface when used only"></span></em></strong></td>
......@@ -321,55 +310,46 @@ VHDL records are not used here, to facilitate integration of the module into Ver
<td align="center">wrf_src_dat_o</td>
<td>out</td>
<td>std_logic_vector</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wrf_src_cyc_o</td>
<td>out</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="even">
<td align="center">wrf_src_stb_o</td>
<td>out</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wrf_src_we_o</td>
<td>out</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="even">
<td align="center">wrf_src_sel_o</td>
<td>out</td>
<td>std_logic_vector</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wrf_src_ack_i</td>
<td>in</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="even">
<td align="center">wrf_src_stall_i</td>
<td>in</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wrf_src_err_i</td>
<td>in</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="even">
<td align="center">wrf_src_rty_i</td>
<td>in</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wrf_snk_adr_i</td>
......@@ -382,55 +362,46 @@ VHDL records are not used here, to facilitate integration of the module into Ver
<td align="center">wrf_snk_dat_i</td>
<td>in</td>
<td>std_logic_vector</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wrf_snk_cyc_i</td>
<td>in</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="even">
<td align="center">wrf_snk_stb_i</td>
<td>in</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wrf_snk_we_i</td>
<td>in</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="even">
<td align="center">wrf_snk_sel_i</td>
<td>in</td>
<td>std_logic_vector</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wrf_snk_ack_o</td>
<td>out</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="even">
<td align="center">wrf_snk_stall_o</td>
<td>out</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="odd">
<td align="center">wrf_snk_err_o</td>
<td>out</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="even">
<td align="center">wrf_snk_rty_o</td>
<td>out</td>
<td>std_logic</td>
<td></td>
</tr>
<tr class="odd">
<td align="center"><strong>WR streamers <em><span class="&quot;streamers&quot;@ = @g_fabric_iface when used only"></span></em></strong></td>
......