Peter clb wrpc v5

There are 3 wr-cores.git branches that are based on each other: peter_clb_wrpc-v5 (SHA-1: 5886ad1e) peter_sit5359_wrpc-v5 (SHA-1: 70ddf23d) peter_wrpc-v5 (SHA-1: 855e86f9)

Some explanation: a) peter_wrpc-v5 contains Toms "Casino" implementation for family7-GTX transceivers (family7-gtx-lp). Tom also implemented this but his implementation is based on usage of QPLL which consumes a full QUAD. In some applications (like SPEC7 v2; see [1]) it is not possible to use a QPLL. Moreover, the statement that a CPLL is worse w.r.t. phase noise is only valid for frequency offsets above 1 MHz as you also can see in [1].

b) SPEC7 uses general-cores "xwb_axi4lite_bridge" which had a small bug that was repaired by Pascal (general-cores.git; wb_axi4lite_bridge_fix; SHA-1: c5599a5)

c) peter_sit5359_wrpc-v5 adds sources for SiTime 5359 MEMs DCTCXO (similar to Silicon Labs Si570). We are going to use them in our BabyWR modules [3]. Apart from better phase noise, these oscillators have a better granularity than the default 16 bits that are used for tuning the DACs that normally drive the WR VCXOs. Therefor I introduced a "g_dac_bits" generic (default 16 of course). However I bumped into an issue with "tm_dac_value" that needs to be increased in size from 24 to 32 bits in order to facilitate wider DAC ranges. I don't think this will be problematic for other designs but this is something to check.

d) peter_clb_wrpc-v5 updates the KM3NeT reference designs and implements low phase drift for CLBv2 and CLBv4.

To summarize: to merge all a list of repo's, branches and SHA codes below

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wr-cores.git: peter_clb_wrpc-v5 (SHA-1: 5886ad1e) <= that is this merge request

Which depends on: general-cores.git: wb_axi4lite_bridge_fix (SHA-1: c5599a5) See another merge request for general-cores.git