- May 22, 2012
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Grzegorz Daniluk authored
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- May 14, 2012
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
The problem was that the WR core did not expose the err and rty lines. If a device ever used these lines (the crossbar does for example), then the master would get hung waiting for an answer.
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changed WR SFP to SFP2
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Wesley W. Terpstra authored
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- May 02, 2012
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- Apr 30, 2012
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- Apr 27, 2012
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Grzegorz Daniluk authored
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- Apr 26, 2012
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Tomasz Wlostowski authored
wr_core: wired clk_aux clock (1 channel), default values for inputs, added tm_link_up_o output and wired aux DAC signals
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Tomasz Wlostowski authored
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- Apr 24, 2012
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Tomasz Wlostowski authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
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- Apr 23, 2012
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- Apr 20, 2012
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- Apr 19, 2012
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Tomasz Wlostowski authored
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- Apr 16, 2012
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
modules/wr_pps_gen: added external PPS input and resynchronization of internal PPS vs external reference and local clock
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- Apr 13, 2012
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Grzegorz Daniluk authored
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- Apr 12, 2012
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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