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Maciej Lipinski authored
It seems that pll_aux_locked is in clk_sys clock domain. When synthesising cute for BTrain I had timing errors in the 10MHz generation process. This commit fixes the timing issues.
4e70a456
It seems that pll_aux_locked is in clk_sys clock domain. When synthesising cute for BTrain I had timing errors in the 10MHz generation process. This commit fixes the timing issues.