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git-svn-id: http://svn.ohwr.org/wishbone-gen@20 4537843c-45c2-4d80-8546-c3283569414f

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git-svn-id: http://svn.ohwr.org/wishbone-gen@20 4537843c-45c2-4d80-8546-c3283569414f
a399be75 · twlostow · d20fa15c · a399be75 · a399be75 · a399be75
Commit a399be75 authored Aug 06, 2010 by twlostow
6 changed files
--- a/cgen_c_headers.lua
+++ b/cgen_c_headers.lua
@@ -197,7 +197,7 @@ function cgen_generate_c_header_code()
   cgen_c_fileheader();
   cgen_c_field_masks();
-   if(options.c_regs_style == "struct") then
+   if(options.c_reg_style == "struct") then
      cgen_c_struct();
   else
      cgen_c_defines();

--- a/lib/wbgen2_eic.vhd
+++ b/lib/wbgen2_eic.vhd
@@ -48,8 +48,12 @@ entity wbgen2_eic is
    rst_n_i : in std_logic;             -- reset & system clock, as always :)
    clk_i   : in std_logic;
-    irq_i : in std_logic_vector(g_num_interrupts-1 downto 0);  -- raw interrupt
+    -- raw interrupt inputs
-                                                               -- inputs
+    irq_i : in std_logic_vector(g_num_interrupts-1 downto 0);  
+    -- interrupt acknowledge signal, used for level-active interrupts to
+    -- indicate that the interrupt has been handled
+    irq_ack_o: out std_logic_vector(g_num_interrupts-1 downto 0);  
 -- interrupt mask regsiter (slv/bus read-only)
    reg_imr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
@@ -149,7 +153,12 @@ begin  -- syn
        if((reg_isr_i(i) = '1' and reg_isr_wr_stb_i = '1') or irq_mask(i) = '0') then
          irq_pending(i) <= '0';
+          irq_i_d0(i) <= '0';
+          irq_i_d1(i) <= '0';
+          irq_i_d2(i) <= '0';
        else
          case irq_mode(i) is
            when c_IRQ_MODE_LEVEL_0      => irq_pending(i) <= not irq_i_d2(i);
            when c_IRQ_MODE_LEVEL_1      => irq_pending(i) <= irq_i_d2(i);
@@ -194,6 +203,10 @@ begin  -- syn
    end if;
  end process;
+  gen_irq_ack: for i in 0 to g_num_interrupts-1 generate
+    irq_ack_o(i) <= '1' when (reg_isr_wr_stb_i = '1' and reg_isr_i(i) = '1') else '0';
+  end generate gen_irq_ack;
  reg_imr_o <= irq_mask;
  reg_isr_o <= irq_pending;

--- a/lib/wbgen2_pkg.vhd
+++ b/lib/wbgen2_pkg.vhd
@@ -70,6 +70,7 @@ package wbgen2_pkg is
      rst_n_i          : in  std_logic;
      clk_i            : in  std_logic;
      irq_i            : in  std_logic_vector(g_num_interrupts-1 downto 0);
+      irq_ack_o        : out std_logic_vector(g_num_interrupts-1 downto 0);
      reg_imr_o        : out std_logic_vector(g_num_interrupts-1 downto 0);
      reg_ier_i        : in  std_logic_vector(g_num_interrupts-1 downto 0);
      reg_ier_wr_stb_i : in  std_logic;

--- a/wbgen2
+++ b/wbgen2
--- a/wbgen_eic.lua
+++ b/wbgen_eic.lua
@@ -75,6 +75,7 @@ function wbgen_generate_eic()
 										["hdl_prefix"] = "EIC_ISR";
 										["signals"] = { signal (SLV, periph.irqcount, "eic_isr_clear_int");
 																		signal (SLV, periph.irqcount, "eic_isr_status_int");
+																		signal (SLV, periph.irqcount, "eic_irq_ack_int");
 																		signal (BIT, 0, "eic_isr_write_int"); };
 										["write_code"] = { va("eic_isr_write_int", 1); };
@@ -126,6 +127,7 @@ function wbgen_generate_eic()
 			["access_dev"] = READ_WRITE;
 		};
 		local field_ier = {
 			["__blockindex"] = irq.index;			
 			["__type"] = TYPE_FIELD;
@@ -168,13 +170,24 @@ function wbgen_generate_eic()
+		irq.full_prefix = string.lower("irq_"..irq.hdl_prefix);
+		irq.ports = { port(BIT, 0, "in", irq.full_prefix.."_i"); };
+		if(irq.ack_line == true) then
+			 table_join(irq.ports, { port(BIT, 0, "out", irq.full_prefix.."_ack_o"); });
+		end
+		if(irq.mask_line == true) then
+			 table_join(irq.ports, { port(BIT, 0, "out", irq.full_prefix.."_mask_o"); });
+		end
 		table.insert(reg_idr, field_idr);
 		table.insert(reg_isr, field_isr);
 		table.insert(reg_imr, field_imr);
 		table.insert(reg_ier, field_ier);
-		irq.full_prefix = string.lower("irq_"..irq.hdl_prefix);
-		irq.ports = { port(BIT, 0, "in", irq.full_prefix.."_i"); };
 	end);
@@ -193,6 +206,7 @@ function wbgen_generate_eic()
 									vpm("clk_i", 							"bus_clock_int");
 									vpm("rst_n_i", 						"rst_n_i");
 									vpm("irq_i", 							"irq_inputs_vector_int");
+									vpm("irq_ack_o", 					"eic_irq_ack_int");
 									vpm("reg_imr_o",					"eic_imr_int");
 									vpm("reg_ier_i",					"eic_ier_int");
 									vpm("reg_ier_wr_stb_i",		"eic_ier_write_int");
@@ -220,8 +234,18 @@ function wbgen_generate_eic()
 	local irq_unit_code = { vinstance("eic_irq_controller_inst", "wbgen2_eic", maps	); };
-	foreach_reg({TYPE_IRQ}, function(irq)
+	foreach_reg({TYPE_IRQ}, 
+							function(irq)
 								 table_join(irq_unit_code, {va(vi("irq_inputs_vector_int", irq.index), irq.full_prefix.."_i")});
+								 if(irq.ack_line == true) then
+										table_join(irq_unit_code, {va(irq.full_prefix.."_ack_o", vi("eic_irq_ack_int", irq.index))});
+								 end
+								 if(irq.mask_line == true) then
+										table_join(irq_unit_code, {va(irq.full_prefix.."_mask_o", vi("eic_imr_int", irq.index))});
+								 end
 							end);
 	local fake_irq = {

--- a/wbgen_regbank.lua
+++ b/wbgen_regbank.lua
@@ -682,6 +682,18 @@ function gen_hdl_code_reg_field(field, reg)
 		gen_hdl_code_constant(field, reg);
 end
+ if(field.ack_read ~= nil) then 
+		table_join(field.ports, { port (BIT, 0, "out", field.ack_read) });
+		table_join(field.read_code, { va(field.ack_read, 1) });
+		if(field.reset_code_main == nil) then field.reset_code_main = {}; end
+		table_join(field.reset_code_main, { va(field.ack_read,  0) });
+		if(field.ackgen_code == nil) then field.ackgen_code= {}; end
+		table_join(field.ackgen_code, { va(field.ack_read, 0) });
+ end
 end
 -- generates VHDL for single register