Commit 72a0f7f0 authored by twlostow's avatar twlostow

bugfixes in FIFO generator, added read notifications

git-svn-id: 4537843c-45c2-4d80-8546-c3283569414f
parent f8ead30c
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......@@ -150,8 +150,12 @@ function calc_size(field, reg)
-- iterates for all registers which type is in "accecepted_types", executing function "func" for each register
function foreach_reg(accepted_types, func)
for i,v in ipairs(periph) do
function foreach_reg(accepted_types, func, p)
if(p == nil) then
p = periph;
for i,v in ipairs(p) do
if(type(v) == 'table') then
if(v.__type ~= nil and (match(v.__type, accepted_types))) then
......@@ -228,6 +228,10 @@ function fifo_wire_bus_ports(fifo)
function gen_fifo_csr_field(flag, field_prefix, field_name, field_desc, size, type, offset)
if(fifo.flags_bus == nil) then
if inset(flag, fifo.flags_bus) then
local f = {
["__type"] = TYPE_FIELD;
......@@ -692,8 +692,6 @@ function gen_hdl_code_reg_field(field, reg)
if(field.ackgen_code == nil) then field.ackgen_code= {}; end
table_join(field.ackgen_code, { va(field.ack_read, 0) });
-- generates VHDL for single register
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