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Wishbone slave generator
Commit 307440ab authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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re-generated squished binary

parent 69883c7c
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Showing with 412 additions and 476 deletions
wbgen2
View file @ 307440ab
#!/usr/bin/env lua
package.preload['alt_getopt']=(function(...)
local n,h,u,o,a=type,pairs,ipairs,io,os
local i,s,u,a,o=type,pairs,ipairs,io,os
module("alt_getopt")
local function i(e)
local t=1
local t=#e
local t={}
for e,a in e:gmatch("(%w)(:?)")do
t[e]=#a
local function r(t)
local e=1
local e=#t
local e={}
for t,a in t:gmatch("(%w)(:?)")do
e[t]=#a
end
return t
return e
end
local function r(e,t)
o.stderr:write(e)
a.exit(t)
local function d(t,e)
a.stderr:write(t)
o.exit(e)
end
local function a(e)
r("Unknown option `-"..
d("Unknown option `-"..
(#e>1 and"-"or"")..e.."'\n",1)
end
local function l(t,e)
if not t[e]then
a(e)
end
while n(t[e])=="string"do
while i(t[e])=="string"do
e=t[e]
if not t[e]then
a(e)
......@@ -31,14 +31,14 @@ end
end
return e
end
function get_ordered_opts(n,a,d)
function get_ordered_opts(n,o,a)
local t=1
local e=1
local o={}
local s={}
local i=i(a)
for t,e in h(d)do
i[t]=e
local i={}
local h={}
local o=r(o)
for e,t in s(a)do
o[e]=t
end
while t<=#n do
local a=n[t]
......@@ -48,49 +48,49 @@ break
elseif a=="-"then
break
elseif a:sub(1,2)=="--"then
local h=a:find("=",1,true)
if h then
local t=a:sub(3,h-1)
t=l(i,t)
if i[t]==0 then
r("Bad usage of option `"..a.."'\n",1)
end
s[e]=a:sub(h+1)
o[e]=t
local s=a:find("=",1,true)
if s then
local t=a:sub(3,s-1)
t=l(o,t)
if o[t]==0 then
d("Bad usage of option `"..a.."'\n",1)
end
h[e]=a:sub(s+1)
i[e]=t
else
local h=a:sub(3)
h=l(i,h)
if i[h]==0 then
o[e]=h
local s=a:sub(3)
s=l(o,s)
if o[s]==0 then
i[e]=s
else
if t==#n then
r("Missed value for option `"..a.."'\n",1)
d("Missed value for option `"..a.."'\n",1)
end
s[e]=n[t+1]
o[e]=h
h[e]=n[t+1]
i[e]=s
t=t+1
end
end
e=e+1
elseif a:sub(1,1)=="-"then
local h
for d=2,a:len()do
local h=l(i,a:sub(d,d))
if i[h]==0 then
o[e]=h
local s
for r=2,a:len()do
local s=l(o,a:sub(r,r))
if o[s]==0 then
i[e]=s
e=e+1
elseif a:len()==d then
elseif a:len()==r then
if t==#n then
r("Missed value for option `-"..h.."'\n",1)
d("Missed value for option `-"..s.."'\n",1)
end
s[e]=n[t+1]
o[e]=h
h[e]=n[t+1]
i[e]=s
t=t+1
e=e+1
break
else
s[e]=a:sub(d+1)
o[e]=h
h[e]=a:sub(r+1)
i[e]=s
e=e+1
break
end
......@@ -100,11 +100,11 @@ break
end
t=t+1
end
return o,t,s
return i,t,h
end
function get_opts(t,a,o)
function get_opts(a,t,o)
local e={}
local t,i,o=get_ordered_opts(t,a,o)
local t,i,o=get_ordered_opts(a,t,o)
for a,t in u(t)do
if o[a]then
e[t]=o[a]
......@@ -191,7 +191,7 @@ t=t+1;
end
return t;
end
function calc_size(e,t)
function calc_size(e,a)
if(e.type==MONOSTABLE or e.type==BIT)then
e.size=1;
elseif(e.type==SLV or e.type==PASS_THROUGH)then
......@@ -212,7 +212,7 @@ end
elseif(e.type==ENUM)then
die("ENUM-type fields are not yet supported. Sorry :(");
end
t.total_size=t.total_size+e.size;
a.total_size=a.total_size+e.size;
end
function foreach_reg(a,t,e)
if(e==nil)then
......@@ -292,15 +292,15 @@ if(t==e)then return true;end
end
return false;
end
function inset(t,e)
for a,e in ipairs(e)do if(t==e)then return true;end end
function inset(e,t)
for a,t in ipairs(t)do if(e==t)then return true;end end
return false;
end
function csel(t,a,e)
if(t)then
function csel(e,a,t)
if(e)then
return a;
else
return e;
return t;
end
end
function check_field_types(e)
......@@ -324,13 +324,13 @@ return e;
end
return e;
end
function default_access(e,t,a,o)
function default_access(e,t,o,a)
if(e.type==t)then
if(e.access_bus==nil)then
e.access_bus=a;
e.access_bus=o;
end
if(e.access_dev==nil)then
e.access_dev=o;
e.access_dev=a;
end
end
end
......@@ -418,11 +418,11 @@ end);
address_bus_width=o+a;
address_bus_select_bits=a;
end
function find_max(e,a)
local t=0;
function find_max(e,t)
local a=0;
local o,o;
for o,e in pairs(e)do if(type(e)=='table'and e[a]~=nil and e[a]>t)then t=e[a];end end
return t;
for o,e in pairs(e)do if(type(e)=='table'and e[t]~=nil and e[t]>a)then a=e[t];end end
return a;
end
function table_join(t,e)
local a,a;
......@@ -432,26 +432,26 @@ table.insert(t,e);
end
end
function tree_2_table(e)
local a={};
foreach_reg({TYPE_REG,TYPE_RAM,TYPE_FIFO,TYPE_IRQ},function(t)
if(t[e]~=nil)then
if(type(t[e])=='table')then
table_join(a,t[e]);
local t={};
foreach_reg({TYPE_REG,TYPE_RAM,TYPE_FIFO,TYPE_IRQ},function(a)
if(a[e]~=nil)then
if(type(a[e])=='table')then
table_join(t,a[e]);
else
table.insert(a,t[e]);
table.insert(t,a[e]);
end
end
foreach_subfield(t,function(t,o)
if(t[e]~=nil)then
if(type(t[e])=='table')then
table_join(a,t[e]);
foreach_subfield(a,function(a,o)
if(a[e]~=nil)then
if(type(a[e])=='table')then
table_join(t,a[e]);
else
table.insert(a,t[e]);
table.insert(t,a[e]);
end
end
end);
end);
return a;
return t;
end
function remove_duplicates(o)
function count_entries(t,a)
......@@ -470,60 +470,60 @@ end
return e;
end
function wbgen_count_subblocks()
local e=0;
local a=0;
local t=0;
local o=0;
local a=0;
foreach_reg({TYPE_RAM},function(t)e=e+1;end);
local e=0;
foreach_reg({TYPE_RAM},function(e)a=a+1;end);
foreach_reg({TYPE_REG},function(e)o=o+1;end);
foreach_reg({TYPE_FIFO},function(e)t=t+1;end);
foreach_reg({TYPE_IRQ},function(e)a=a+1;end);
periph.ramcount=e;
foreach_reg({TYPE_IRQ},function(t)e=e+1;end);
periph.ramcount=a;
periph.fifocount=t;
periph.regcount=o;
periph.irqcount=a;
if(e+t+o+a==0)then
periph.irqcount=e;
if(a+t+o+e==0)then
die("Can't generate an empty peripheral. Define some regs, RAMs, FIFOs or IRQs, please...");
end
end
function deepcopy(i)
local o={}
local function a(e)
local a={}
local function t(e)
if type(e)~="table"then
return e
elseif o[e]then
return o[e]
elseif a[e]then
return a[e]
end
local t={}
o[e]=t
for o,e in pairs(e)do
t[a(o)]=a(e)
local o={}
a[e]=o
for a,e in pairs(e)do
o[t(a)]=t(e)
end
return setmetatable(t,getmetatable(e))
return setmetatable(o,getmetatable(e))
end
return a(i)
return t(i)
end
function va(a,t)
function va(t,a)
local e={};
e.t="assign";
e.dst=a;
e.src=t;
e.dst=t;
e.src=a;
return e;
end
function vi(t,o,a)
function vi(a,o,t)
local e={};
e.t="index";
e.name=t;
e.name=a;
e.h=o;
e.l=a;
e.l=t;
return e;
end
function vinstance(a,t,o)
function vinstance(o,t,a)
local e={};
e.t="instance";
e.name=a;
e.name=o;
e.component=t;
e.maps=o;
e.maps=a;
return e;
end
function vpm(a,t)
......@@ -533,33 +533,33 @@ e.to=a;
e.from=t;
return e;
end
function vgm(a,t)
function vgm(t,a)
local e={};
e.t="genmap";
e.to=a;
e.from=t;
e.to=t;
e.from=a;
return e;
end
function vcombprocess(a,t)
function vcombprocess(t,a)
local e={};
e.t="combprocess";
e.slist=a;
e.code=t;
e.slist=t;
e.code=a;
return e;
end
function vsyncprocess(a,o,t)
function vsyncprocess(t,a,o)
local e={};
e.t="syncprocess";
e.clk=a;
e.rst=o;
e.code=t;
e.clk=t;
e.rst=a;
e.code=o;
return e;
end
function vreset(t,a)
function vreset(a,t)
local e={};
e.t="reset";
e.level=t;
e.code=a;
e.level=a;
e.code=t;
return e;
end
function vposedge(t)
......@@ -583,18 +583,18 @@ e.cond={t};
e.code=a;
return e;
end
function vequal(a,t)
function vequal(t,a)
local e={};
e.t="eq";
e.a=a;
e.b=t;
e.a=t;
e.b=a;
return e;
end
function vand(t,a)
function vand(a,t)
local e={};
e.t="and";
e.a=t;
e.b=a;
e.a=a;
e.b=t;
return e;
end
function vor(a,t)
......@@ -610,18 +610,18 @@ e.t="not";
e.a=t;
return e;
end
function vswitch(a,t)
function vswitch(t,a)
local e={};
e.t="switch";
e.a=a;
e.code=t;
e.a=t;
e.code=a;
return e;
end
function vcase(a,t)
function vcase(t,a)
local e={};
e.t="case";
e.a=a;
e.code=t;
e.a=t;
e.code=a;
return e;
end
function vcasedefault(t)
......@@ -636,11 +636,11 @@ e.t="comment";
e.str=t;
return e;
end
function vsub(a,t)
function vsub(t,a)
local e={};
e.t="sub";
e.a=a;
e.b=t;
e.a=t;
e.b=a;
return e;
end
function vothers(t)
......@@ -734,17 +734,17 @@ table_join(e,tree_2_table("ports"));
return e;
end
function cgen_build_optional_list()
local a={}
local o={}
local a={}
local t=1
for i,e in pairs(tree_2_table("optional"))do
if a[e]==nil then
a[e]=1
o[t]=e
if o[e]==nil then
o[e]=1
a[t]=e
t=t+1
end
end
return o
return a
end
function cgen_find_sigport(e)
for a,t in pairs(g_portlist)do if(e==t.name)then return t;end end
......@@ -838,63 +838,45 @@ fieldtype_2_vhdl[SIGNED]="signed";
fieldtype_2_vhdl[UNSIGNED]="unsigned";
fieldtype_2_vhdl[ENUM]="std_logic_vector";
fieldtype_2_vhdl[SLV]="std_logic_vector";
function get_pkg_name()
if(periph.hdl_package)then
return periph.hdl_package
else
return periph.hdl_prefix.."_wbgen2_pkg";
end
end
function gen_vhdl_bin_literal(i,o)
if(o==1)then
return string.format("'%d'",csel(i==0,0,1));
end
local t='\"';
local s,a,n,e;
local e='\"';
local s,a,n,t;
a=i;
e=math.pow(2,o-1);
t=math.pow(2,o-1);
if(i==nil)then
for e=1,o do
t=t.."X";
for t=1,o do
e=e.."X";
end
else
for o=1,o do
n=math.floor(a/e);
t=t..csel(n>0,"1","0");
a=a%e;
e=e/2;
n=math.floor(a/t);
e=e..csel(n>0,"1","0");
a=a%t;
t=t/2;
end
end
return t..'\"';
return e..'\"';
end
function strip_periph_prefix(e)
return string.gsub(e,"^"..periph.hdl_prefix.."\_","")
end
function strip_wb_prefix(e)
local e=string.gsub(e,"^wb\_","")
e=string.gsub(e,"_o$","")
e=string.gsub(e,"_i$","")
return e
end
function port2record(e)
if(options.hdl_reg_style=="signals")then
if(options.hdl_reg_style~="record")then
return e
end
for a,t in ipairs(g_portlist)do
if(t.name==e and t.is_reg_port)then
return csel(t.dir=="in","regs_i.","regs_o.")..strip_periph_prefix(e)
end
if(t.name==e and t.is_wb and options.hdl_reg_style=="record_full")then
if e=="wb_int_o"then
return"int_o";
end
return csel(t.dir=="in","slave_i.","slave_o.")..strip_wb_prefix(e)
end
end
return e
end
function cgen_vhdl_package()
emit("package "..get_pkg_name().." is")
local t=periph.hdl_prefix.."_wbgen2_pkg";
emit("package "..t.." is")
indent_right();
emit("");
emit("");
......@@ -905,62 +887,39 @@ emit("");
emit("-- Output registers (WB slave -> user design)");
emit("");
cgen_vhdl_port_struct("out");
indent_left();
local e="t_"..periph.hdl_prefix.."_in_registers";
emit("");
emit("function \"or\" (left, right: "..e..") return "..e..";");
emit("function f_x_to_zero (x:std_logic) return std_logic;");
emit("function f_x_to_zero (x:std_logic_vector) return std_logic_vector;");
emit("");
cgen_vhdl_interface_declaration("component")
indent_left();
indent_left();
emit("end package;");
emit("");
emit("package body "..get_pkg_name().." is");
indent_right();
emit("package body "..t.." is");
emit("function f_x_to_zero (x:std_logic) return std_logic is");
emit("begin")
indent_right();
emit("if x = '1' then")
indent_right();
emit("return '1';")
indent_left();
emit("else")
indent_right();
emit("return '0';")
indent_left();
emit("end if;")
indent_left();
emit("end function;");
emit("")
emit("function f_x_to_zero (x:std_logic_vector) return std_logic_vector is");
indent_right();
emit("variable tmp: std_logic_vector(x'length-1 downto 0);");
indent_left();
emit("begin");
indent_right();
emit("for i in 0 to x'length-1 loop");
indent_right();
emit("if(x(i) = 'X' or x(i) = 'U') then");
indent_right();
emit("tmp(i):= '0';");
indent_left();
emit("if(x(i) = '1') then");
emit("tmp(i):= '1';");
emit("else");
indent_right();
emit("tmp(i):=x(i);");
indent_left();
emit("tmp(i):= '0';");
emit("end if; ");
indent_left();
emit("end loop; ");
emit("return tmp;");
indent_left();
emit("end function;");
emit("");
emit("function \"or\" (left, right: "..e..") return "..e.." is");
indent_right();
emit("variable tmp: "..e..";");
indent_left();
emit("begin");
indent_right();
for e=1,table.getn(g_portlist)do
local e=g_portlist[e];
if(e.is_reg_port==true and e.dir=="in")then
......@@ -969,10 +928,7 @@ emit("tmp."..e.." := f_x_to_zero(left."..e..") or f_x_to_zero(right."..e..");");
end
end
emit("return tmp;");
indent_left();
emit("end function;");
indent_left();
emit("");
emit("end package body;");
end
function cgen_vhdl_port_struct(o)
......@@ -994,8 +950,8 @@ end
t=t..";";
emit(t);
end
indent_left();
emit("end record;");
indent_left();
emit("");
emit("constant c_"..periph.hdl_prefix.."_"..o.."_registers_init_value: t_"..periph.hdl_prefix.."_"..o.."_registers := (");
indent_right();
......@@ -1012,7 +968,6 @@ line=line..",";
end
emit(line);
end
indent_left();
emit(");");
end
function cgen_vhdl_header(e)
......@@ -1037,22 +992,24 @@ emit("use ieee.numeric_std.all;");
if(periph.ramcount>0 or periph.fifocount>0 or periph.irqcount>0)then
emit("use work.wbgen2_pkg.all;");
end
if(options.hdl_reg_style=="record_full")then
emit("use work.wishbone_pkg.all;");
end
emit("");
end
function cgen_vhdl_interface_declaration(o)
emit(o.." "..periph.hdl_entity.." is");
function cgen_vhdl_entity()
local e;
if(options.hdl_reg_style=="record")then
emit("use work."..periph.hdl_prefix.."_wbgen2_pkg.all;");
emit("\n");
end
emit("entity "..periph.hdl_entity.." is");
indent_right();
if(table.getn(g_optlist)~=0)then
emit("generic (");
indent_right();
emiti()
for e,t in pairs(g_optlist)do
for t,e in pairs(g_optlist)do
emiti();
emitx(t.." : integer := 1");
if(e~=table.getn(g_optlist))then
emitx(e.." : integer := 1");
if(t~=table.getn(g_optlist))then
emit(";")
else
emit(");")
......@@ -1066,13 +1023,7 @@ emit("port (");
indent_right();
for a=1,table.getn(g_portlist)do
local e=g_portlist[a];
local t=true;
if(options.hdl_reg_style=="record"and e.is_reg_port)then
t=false;
elseif(options.hdl_reg_style=="record_full"and(e.is_reg_port or e.is_wb))then
t=false;
end
if(t)then
if(options.hdl_reg_style=="signals"or not e.is_reg_port)then
if(e.comment~=nil and e.comment~="")then
emitx("-- "..e.comment.."\n");
end
......@@ -1080,36 +1031,19 @@ local t=string.format("%-40s : %-6s %s",e.name,e.dir,fieldtype_2_vhdl[e.type]);
if(e.range>1 or e.type==SLV)then
t=t.."("..(e.range-1).." downto 0)";
end
t=t..csel((a==table.getn(g_portlist))and not(options.hdl_reg_style=="record"or options.hdl_reg_style=="record_full"),"",";");
t=t..csel((a==table.getn(g_portlist))and not(options.hdl_reg_style=="record"),"",";");
emit(t);
end
end
if(options.hdl_reg_style=="record_full")then
emit(string.format("%-40s : %-6s %s;","slave_i","in","t_wishbone_slave_in"));
emit(string.format("%-40s : %-6s %s;","slave_o","out","t_wishbone_slave_out"));
emit(string.format("%-40s : %-6s %s;","int_o","out","std_logic"));
end
if(options.hdl_reg_style=="record"or options.hdl_reg_style=="record_full")then
emit(string.format("%-40s : %-6s %s;","regs_i","in","t_"..periph.hdl_prefix.."_in_registers"));
if(options.hdl_reg_style=="record")then
emit(string.format("%-40s : %-6s %s","regs_i","in","t_"..periph.hdl_prefix.."_in_registers;"));
emit(string.format("%-40s : %-6s %s","regs_o","out","t_"..periph.hdl_prefix.."_out_registers"));
end
indent_left();
emit(");");
indent_left();
if(o=="component")then
emit("end component;");
else
emit("end "..periph.hdl_entity..";");
end
emit("");
end
function cgen_vhdl_entity()
local e;
if(options.hdl_reg_style=="record"or options.hdl_reg_style=="record_full")then
emit("use work."..get_pkg_name()..".all;");
emit("\n");
end
cgen_vhdl_interface_declaration("entity")
emit("architecture syn of "..periph.hdl_entity.." is");
emit("");
for t,e in pairs(g_siglist)do
......@@ -1177,22 +1111,22 @@ emit("end process;");
emit("");
emit("");
end
function cgen_vhdl_combprocess(e)
local t=true;
function cgen_vhdl_combprocess(t)
local e=true;
emiti();
emitx("process (");
for a,e in pairs(e.slist)do
if(t)then
t=false;
for a,t in pairs(t.slist)do
if(e)then
e=false;
else
emitx(", ");
end
emitx(e);
emitx(t);
end
emit(")");
emit("begin");
indent_right();
recurse(e.code);
recurse(t.code);
indent_left();
emit("end process;");
emit("");
......@@ -1394,25 +1328,25 @@ end
emit("end case;");
end
function cgen_vhdl_instance(t)
local a=0;
local o=0;
local a=0;
local e;
emit(t.name.." : "..t.component);
for t,e in pairs(t.maps)do
if(e.t=="genmap")then
o=o+1;
elseif(e.t=="portmap")then
a=a+1;
elseif(e.t=="portmap")then
o=o+1;
end
end
if(o>0)then
if(a>0)then
indent_right();
emit("generic map (");
indent_right();
e=1;
for a,t in pairs(t.maps)do
for o,t in pairs(t.maps)do
if(t.t=="genmap")then
emit(string.format("%-20s => %s",t.to,t.from)..csel(e==o,"",","));
emit(string.format("%-20s => %s",t.to,t.from)..csel(e==a,"",","));
e=e+1;
end
end
......@@ -1420,15 +1354,15 @@ indent_left();
emit(")");
indent_left();
end
if(a>0)then
if(o>0)then
indent_right();
emit("port map (");
indent_right();
e=1;
for o,t in pairs(t.maps)do
for a,t in pairs(t.maps)do
if(t.t=="portmap")then
local o=node_typesize(t.from);
emit(string.format("%-20s => %s",t.to,gen_subrange(o))..csel(e==a,"",","));
local a=node_typesize(t.from);
emit(string.format("%-20s => %s",t.to,gen_subrange(a))..csel(e==o,"",","));
e=e+1;
end
end
......@@ -1475,7 +1409,7 @@ t(e);
end
end
end
if((options.hdl_reg_style=="record"or options.hdl_reg_style=="record_full")and options.output_package_file~=nil)then
if(options.hdl_reg_style=="record"and options.output_package_file~=nil)then
cgen_generate_init(options.output_package_file);
cgen_new_snippet();
cgen_vhdl_header(options.output_package_file);
......@@ -1564,7 +1498,7 @@ function cgen_verilog_ending()
indent_left();
emit("endmodule");
end
function cgen_generate_verilog_code(i)
function cgen_generate_verilog_code(n)
local a=false;
function find_code(e,t)
for a,e in ipairs(e)do if((e.t~=nil)and(e.t==t))then return e;end end
......@@ -1720,22 +1654,22 @@ else
emitx(gen_subrange(t));
end
end
function cgen_verilog_binary_op(t)
local o=node_typesize(t.a);
local a=node_typesize(t.b);
local e=t.t;
function cgen_verilog_binary_op(e)
local o=node_typesize(e.a);
local a=node_typesize(e.b);
local t=e.t;
if(o.type==EXPRESSION)then
emitx("(");recurse({t.a});emitx(")");
emitx("(");recurse({e.a});emitx(")");
else
emitx(gen_subrange(o));
end
if(e=="eq")then emitx(" == ");end
if(e=="and")then emitx(" && ");end
if(e=="or")then emitx(" || ");end
if(e=="sub")then emitx(" - ");end
if(e=="add")then emitx(" + ");end
if(t=="eq")then emitx(" == ");end
if(t=="and")then emitx(" && ");end
if(t=="or")then emitx(" || ");end
if(t=="sub")then emitx(" - ");end
if(t=="add")then emitx(" + ");end
if(a.type==EXPRESSION)then
emitx("(");recurse({t.b});emitx(")");
emitx("(");recurse({e.b});emitx(")");
else
emitx(gen_subrange(a));
end
......@@ -1769,29 +1703,29 @@ end
end
emit("endcase");
end
function cgen_verilog_instance(t)
local a=0;
function cgen_verilog_instance(a)
local o=0;
local i=0;
local e;
emitx(t.component.." ");
for t,e in pairs(t.maps)do
emitx(a.component.." ");
for t,e in pairs(a.maps)do
if(e.t=="genmap")then
o=o+1;
i=i+1;
elseif(e.t=="portmap")then
a=a+1;
o=o+1;
end
end
if(o>0)then
if(i>0)then
indent_right();
emit("# (");
indent_right();
e=1;
for t,a in pairs(t.maps)do
for t,a in pairs(a.maps)do
if(a.t=="genmap")then
local t=a.from;
if(t=="true")then t=1;
elseif(t=="false")then t=0;end
emit(string.format(".%-20s(%s)",a.to,t)..csel(e==o,"",","));
emit(string.format(".%-20s(%s)",a.to,t)..csel(e==i,"",","));
e=e+1;
end
end
......@@ -1799,15 +1733,15 @@ indent_left();
emit(")");
indent_left();
end
if(a>0)then
if(o>0)then
indent_right();
emit(t.name.." ( ");
emit(a.name.." ( ");
indent_right();
e=1;
for o,t in pairs(t.maps)do
for a,t in pairs(a.maps)do
if(t.t=="portmap")then
local o=node_typesize(t.from);
emit(string.format(".%-20s(%s)",t.to,gen_subrange(o))..csel(e==a,"",","));
local a=node_typesize(t.from);
emit(string.format(".%-20s(%s)",t.to,gen_subrange(a))..csel(e==o,"",","));
e=e+1;
end
end
......@@ -1876,7 +1810,7 @@ cgen_new_snippet();
cgen_verilog_header();
local a=cgen_get_snippet();
cgen_new_snippet();
recurse(i);
recurse(n);
cgen_verilog_ending();
local e=cgen_get_snippet();
cgen_new_snippet();
......@@ -2127,39 +2061,39 @@ if(t.ports~=nil)then return true;end
foreach_subfield(t,function(t)if(t.ports~=nil)then e=true;end end);
return e;
end
function htable_add_row(e,a)
if(a>e.rows)then
for t=e.rows+1,a do
function htable_add_row(e,t)
if(t>e.rows)then
for t=e.rows+1,t do
e.data[t]={};
for a=1,e.cols do
e.data[t][a]={};
e.data[t][a].text="";
end
end
e.rows=a;
e.rows=t;
end
end
function hlink(t,e)
return'<A href="'..t..'">'..e..'</a>';
function hlink(e,t)
return'<A href="'..e..'">'..t..'</a>';
end
function hitem(e)
return'<li>'..e..'</li>';
end
function hanchor(t,e)
return'<a name="'..t..'">'..e..'</a>';
function hanchor(e,t)
return'<a name="'..e..'">'..t..'</a>';
end
doc_toc={};
function hsection(a,t,o)
function hsection(t,a,o)
local e={};
local i=0;
e.id_mangled="sect_"..a.."_"..t;
e.key=a*1e3+t;
if(t~=0)then
e.id_mangled="sect_"..t.."_"..a;
e.key=t*1e3+a;
if(a~=0)then
e.level=2;
e.id=a.."."..t..".";
e.id=t.."."..a..".";
else
e.level=1;
e.id=a..".";
e.id=t..".";
end
e.name=o;
table.insert(doc_toc,e);
......@@ -2208,9 +2142,9 @@ end
end);
cgen_doc_symbol(t);
end
function cgen_doc_mem_symbol(a)
function cgen_doc_mem_symbol(e)
local t={};
for e,a in pairs(a.ports)do
for e,a in pairs(e.ports)do
local e=a;
if(string.find(a.name,"_i")~=nil)then
e.is_wb=true;
......@@ -2219,8 +2153,8 @@ e.is_wb=false;
end
table.insert(t,e);
end
if(a.clock~=nil)then
local e=port(BIT,0,"in",a.clock);
if(e.clock~=nil)then
local e=port(BIT,0,"in",e.clock);
e.is_wb=true;
table.insert(t,e);
end
......@@ -2285,7 +2219,7 @@ local e=periph.description;
if(e==nil)then e="";end
emit('<p>'..string.gsub(e,"\n","<br>")..'</p>');
emit('<h3>Contents:</h3>');
table.sort(doc_toc,function(e,t)return e.key<t.key;end);
table.sort(doc_toc,function(t,e)return t.key<e.key;end);
for t,e in ipairs(doc_toc)do
emit('<span style="margin-left: '..((e.level-1)*20)..'px; ">'..e.id.." "..hlink('#'..e.id_mangled,e.name)..'</span><br/>');
end
......@@ -2322,19 +2256,19 @@ e[5].text=string.upper(t.c_prefix);
i=not i;
end
end);
foreach_reg({TYPE_RAM},function(t)
if(t.full_hdl_prefix~=nil)then
foreach_reg({TYPE_RAM},function(e)
if(e.full_hdl_prefix~=nil)then
htable_add_row(o,a);
local e=o.data[a];a=a+1;
e.style=csel(i,"tr_odd","tr_even");
e[1].style="td_code";
e[1].text=string.format("0x%x - 0x%x",t.base,t.base+math.pow(2,t.wrap_bits)*t.size-1);
e[2].text="MEM";
e[3].text=hlink("#"..string.upper(t.c_prefix),t.name);
e[4].style="td_code";
e[4].text=t.full_hdl_prefix;
e[5].style="td_code";
e[5].text=string.upper(t.c_prefix);
local t=o.data[a];a=a+1;
t.style=csel(i,"tr_odd","tr_even");
t[1].style="td_code";
t[1].text=string.format("0x%x - 0x%x",e.base,e.base+math.pow(2,e.wrap_bits)*e.size-1);
t[2].text="MEM";
t[3].text=hlink("#"..string.upper(e.c_prefix),e.name);
t[4].style="td_code";
t[4].text=e.full_hdl_prefix;
t[5].style="td_code";
t[5].text=string.upper(e.c_prefix);
i=not i;
end
end);
......@@ -2482,26 +2416,26 @@ emit("<p>"..string.gsub(t.description,"\n","<br>").."</p>");
end
end
cur_irq_no=1;
function cgen_doc_irq(e)
emit(hanchor(string.upper(e.c_prefix),""));
emit(hsection(5,cur_irq_no,e.name));
function cgen_doc_irq(t)
emit(hanchor(string.upper(t.c_prefix),""));
emit(hsection(5,cur_irq_no,t.name));
cur_irq_no=cur_irq_no+1;
local t=htable_new(3,2);
t.data[1][1].text="<b>HW prefix: </b>";
t.data[2][1].text="<b>C prefix: </b>";
t.data[3][1].text="<b>Trigger: </b>";
t.data[1][2].text=string.lower(periph.hdl_prefix.."_"..e.hdl_prefix);
t.data[2][2].text=string.upper(e.c_prefix);
local e=htable_new(3,2);
e.data[1][1].text="<b>HW prefix: </b>";
e.data[2][1].text="<b>C prefix: </b>";
e.data[3][1].text="<b>Trigger: </b>";
e.data[1][2].text=string.lower(periph.hdl_prefix.."_"..t.hdl_prefix);
e.data[2][2].text=string.upper(t.c_prefix);
local a={
[EDGE_RISING]="rising edge";
[EDGE_FALLING]="falling edge";
[LEVEL_0]="low level";
[LEVEL_1]="high level";
};
t.data[3][2].text=a[e.trigger];
htable_emit(t);
if(e.description~=nil)then
emit("<p>"..string.gsub(e.description,"\n","<br>").."</p>");
e.data[3][2].text=a[t.trigger];
htable_emit(e);
if(t.description~=nil)then
emit("<p>"..string.gsub(t.description,"\n","<br>").."</p>");
end
end
function cgen_generate_html_documentation()
......@@ -2510,19 +2444,19 @@ cgen_new_snippet();
emit(hsection(3,0,"Register description"));
foreach_reg({TYPE_REG},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_reg(e);end end);
local o=cgen_get_snippet();
local a="";
local t="";
if(periph.ramcount>0)then
emit(hsection(4,0,"Memory blocks"));
cgen_new_snippet();
foreach_reg({TYPE_RAM},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_ram(e);end end);
a=cgen_get_snippet();
t=cgen_get_snippet();
end
local t="";
local a="";
if(periph.irqcount>0)then
cgen_new_snippet();
emit(hsection(5,0,"Interrupts"));
foreach_reg({TYPE_IRQ},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_irq(e);end end);
t=cgen_get_snippet();
a=cgen_get_snippet();
end
cgen_new_snippet();
cgen_doc_memmap();
......@@ -2532,8 +2466,8 @@ cgen_doc_header_and_toc();
emit(e);
emit(i);
emit(o);
emit(a);
emit(t);
emit(a);
emit('</BODY>');
emit('</HTML>');
cgen_write_current_snippet();
......@@ -3050,163 +2984,163 @@ t.ackgen_code_pre={va(e.."_int",e.."_int_delay");
va(e.."_int_delay",0);};
end
end
function gen_hdl_code_bit(t,a)
local e=gen_hdl_field_prefix(t,a);
t.prefix=e;
if(t.clock==nil)then
if(t.access==ACC_RW_RO)then
t.ports={port(BIT,0,"out",e.."_o","Port for BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
t.signals={signal(BIT,0,e.."_int")};
t.acklen=1;
t.write_code={
va(e.."_int",vi("wrdata_reg",t.offset))};
t.read_code={va(vi("rddata_reg",t.offset),e.."_int")};
t.reset_code_main={va(e.."_int",csel(t.reset_value==nil,0,t.reset_value))};
t.extra_code={va(e.."_o",e.."_int")};
elseif(t.access==ACC_RO_WO)then
t.ports={port(BIT,0,"in",e.."_i","Port for BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
t.signals={};
t.acklen=1;
t.write_code={};
t.read_code={va(vi("rddata_reg",t.offset),e.."_i")};
t.reset_code_main={};
t.extra_code={};
elseif(t.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..t.name..")");
elseif(t.access==ACC_RW_RW)then
if(t.load==LOAD_EXT)then
t.ports={port(BIT,0,"out",e.."_o","Ports for BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG),
port(BIT,0,"in",e.."_i",nil,VPORT_REG),
port(BIT,0,"out",e.."_load_o",nil,VPORT_REG)};
t.acklen=1;
t.read_code={va(vi("rddata_reg",t.offset),e.."_i")};
t.write_code={
va(e.."_load_o",1)};
t.extra_code={va(e.."_o",vi("wrdata_reg",t.offset))};
t.ackgen_code_pre={va(e.."_load_o",0)};
t.ackgen_code={va(e.."_load_o",0)};
t.reset_code_main={va(e.."_load_o",0)};
function gen_hdl_code_bit(e,a)
local t=gen_hdl_field_prefix(e,a);
e.prefix=t;
if(e.clock==nil)then
if(e.access==ACC_RW_RO)then
e.ports={port(BIT,0,"out",t.."_o","Port for BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={signal(BIT,0,t.."_int")};
e.acklen=1;
e.write_code={
va(t.."_int",vi("wrdata_reg",e.offset))};
e.read_code={va(vi("rddata_reg",e.offset),t.."_int")};
e.reset_code_main={va(t.."_int",csel(e.reset_value==nil,0,e.reset_value))};
e.extra_code={va(t.."_o",t.."_int")};
elseif(e.access==ACC_RO_WO)then
e.ports={port(BIT,0,"in",t.."_i","Port for BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={};
e.acklen=1;
e.write_code={};
e.read_code={va(vi("rddata_reg",e.offset),t.."_i")};
e.reset_code_main={};
e.extra_code={};
elseif(e.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..e.name..")");
elseif(e.access==ACC_RW_RW)then
if(e.load==LOAD_EXT)then
e.ports={port(BIT,0,"out",t.."_o","Ports for BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG),
port(BIT,0,"in",t.."_i",nil,VPORT_REG),
port(BIT,0,"out",t.."_load_o",nil,VPORT_REG)};
e.acklen=1;
e.read_code={va(vi("rddata_reg",e.offset),t.."_i")};
e.write_code={
va(t.."_load_o",1)};
e.extra_code={va(t.."_o",vi("wrdata_reg",e.offset))};
e.ackgen_code_pre={va(t.."_load_o",0)};
e.ackgen_code={va(t.."_load_o",0)};
e.reset_code_main={va(t.."_load_o",0)};
else
die("internal RW/RW register storage unsupported yet ("..t.name..")");
die("internal RW/RW register storage unsupported yet ("..e.name..")");
end
end
else
if(t.access==ACC_RW_RO)then
t.ports={port(BIT,0,"out",e.."_o","Port for asynchronous (clock: "..t.clock..") BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
t.signals={signal(BIT,0,e.."_int"),
signal(BIT,0,e.."_sync0"),
signal(BIT,0,e.."_sync1")};
t.acklen=4;
t.write_code={va(e.."_int",vi("wrdata_reg",t.offset))};
t.read_code={va(vi("rddata_reg",t.offset),e.."_int")};
t.reset_code_main={va(e.."_int",csel(t.reset_value==nil,0,t.reset_value))};
t.extra_code={vcomment("synchronizer chain for field : "..t.name.." (type RW/RO, clk_sys_i <-> "..t.clock..")");
vsyncprocess(t.clock,"rst_n_i",{
if(e.access==ACC_RW_RO)then
e.ports={port(BIT,0,"out",t.."_o","Port for asynchronous (clock: "..e.clock..") BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={signal(BIT,0,t.."_int"),
signal(BIT,0,t.."_sync0"),
signal(BIT,0,t.."_sync1")};
e.acklen=4;
e.write_code={va(t.."_int",vi("wrdata_reg",e.offset))};
e.read_code={va(vi("rddata_reg",e.offset),t.."_int")};
e.reset_code_main={va(t.."_int",csel(e.reset_value==nil,0,e.reset_value))};
e.extra_code={vcomment("synchronizer chain for field : "..e.name.." (type RW/RO, clk_sys_i <-> "..e.clock..")");
vsyncprocess(e.clock,"rst_n_i",{
vreset(0,{
va(e.."_o",csel(t.reset_value==nil,0,t.reset_value));
va(e.."_sync0",csel(t.reset_value==nil,0,t.reset_value));
va(e.."_sync1",csel(t.reset_value==nil,0,t.reset_value));
va(t.."_o",csel(e.reset_value==nil,0,e.reset_value));
va(t.."_sync0",csel(e.reset_value==nil,0,e.reset_value));
va(t.."_sync1",csel(e.reset_value==nil,0,e.reset_value));
});
vposedge({
va(e.."_sync0",e.."_int");
va(e.."_sync1",e.."_sync0");
va(e.."_o",e.."_sync1");
va(t.."_sync0",t.."_int");
va(t.."_sync1",t.."_sync0");
va(t.."_o",t.."_sync1");
});
});
};
elseif(t.access==ACC_RO_WO)then
t.ports={port(BIT,0,"in",e.."_i","Port for asynchronous (clock: "..t.clock..") BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
t.signals={signal(BIT,0,e.."_sync0"),
signal(BIT,0,e.."_sync1")};
t.acklen=1;
t.write_code={};
t.read_code={va(vi("rddata_reg",t.offset),e.."_sync1")};
t.reset_code_main={};
t.extra_code={vcomment("synchronizer chain for field : "..t.name.." (type RO/WO, "..t.clock.." -> clk_sys_i)");
vsyncprocess(t.clock,"rst_n_i",{
elseif(e.access==ACC_RO_WO)then
e.ports={port(BIT,0,"in",t.."_i","Port for asynchronous (clock: "..e.clock..") BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={signal(BIT,0,t.."_sync0"),
signal(BIT,0,t.."_sync1")};
e.acklen=1;
e.write_code={};
e.read_code={va(vi("rddata_reg",e.offset),t.."_sync1")};
e.reset_code_main={};
e.extra_code={vcomment("synchronizer chain for field : "..e.name.." (type RO/WO, "..e.clock.." -> clk_sys_i)");
vsyncprocess(e.clock,"rst_n_i",{
vreset(0,{
va(e.."_sync0",0);
va(e.."_sync1",0);
va(t.."_sync0",0);
va(t.."_sync1",0);
});
vposedge({
va(e.."_sync0",e.."_i");
va(e.."_sync1",e.."_sync0");
va(t.."_sync0",t.."_i");
va(t.."_sync1",t.."_sync0");
});
});
};
elseif(t.access==ACC_RW_RW)then
if(t.load~=LOAD_EXT)then
elseif(e.access==ACC_RW_RW)then
if(e.load~=LOAD_EXT)then
die("Only external load is supported for RW/RW bit fields");
end
local a="Ports for asynchronous (clock: "..t.clock..") RW/RW BIT field: '"..t.name.."' in reg: '"..a.name.."'";
t.ports={port(BIT,0,"out",e.."_o",a,VPORT_REG),
port(BIT,0,"in",e.."_i",nil,VPORT_REG),
port(BIT,0,"out",e.."_load_o",nil,VPORT_REG)};
t.signals={signal(BIT,0,e.."_int_read"),
signal(BIT,0,e.."_int_write"),
signal(BIT,0,e.."_lw"),
signal(BIT,0,e.."_lw_delay"),
signal(BIT,0,e.."_lw_read_in_progress"),
signal(BIT,0,e.."_lw_s0"),
signal(BIT,0,e.."_lw_s1"),
signal(BIT,0,e.."_lw_s2"),
signal(BIT,0,e.."_rwsel")};
t.acklen=6;
t.write_code={
va(e.."_int_write",vi("wrdata_reg",t.offset));
va(e.."_lw",1);
va(e.."_lw_delay",1);
va(e.."_lw_read_in_progress",0);
va(e.."_rwsel",1);};
t.read_code={vif(vequal("wb_we_i",0),{
va(vi("rddata_reg",t.offset),vundefined());
va(e.."_lw",1);
va(e.."_lw_delay",1);
va(e.."_lw_read_in_progress",1);
va(e.."_rwsel",0);});};
t.reset_code_main={va(e.."_lw",0);
va(e.."_lw_delay",0);
va(e.."_lw_read_in_progress",0);
va(e.."_rwsel",0);
va(e.."_int_write",0);
local a="Ports for asynchronous (clock: "..e.clock..") RW/RW BIT field: '"..e.name.."' in reg: '"..a.name.."'";
e.ports={port(BIT,0,"out",t.."_o",a,VPORT_REG),
port(BIT,0,"in",t.."_i",nil,VPORT_REG),
port(BIT,0,"out",t.."_load_o",nil,VPORT_REG)};
e.signals={signal(BIT,0,t.."_int_read"),
signal(BIT,0,t.."_int_write"),
signal(BIT,0,t.."_lw"),
signal(BIT,0,t.."_lw_delay"),
signal(BIT,0,t.."_lw_read_in_progress"),
signal(BIT,0,t.."_lw_s0"),
signal(BIT,0,t.."_lw_s1"),
signal(BIT,0,t.."_lw_s2"),
signal(BIT,0,t.."_rwsel")};
e.acklen=6;
e.write_code={
va(t.."_int_write",vi("wrdata_reg",e.offset));
va(t.."_lw",1);
va(t.."_lw_delay",1);
va(t.."_lw_read_in_progress",0);
va(t.."_rwsel",1);};
e.read_code={vif(vequal("wb_we_i",0),{
va(vi("rddata_reg",e.offset),vundefined());
va(t.."_lw",1);
va(t.."_lw_delay",1);
va(t.."_lw_read_in_progress",1);
va(t.."_rwsel",0);});};
e.reset_code_main={va(t.."_lw",0);
va(t.."_lw_delay",0);
va(t.."_lw_read_in_progress",0);
va(t.."_rwsel",0);
va(t.."_int_write",0);
};
t.ackgen_code_pre={va(e.."_lw",e.."_lw_delay");
va(e.."_lw_delay",0);
vif(vand(vequal(vi("ack_sreg",1),1),vequal(e.."_lw_read_in_progress",1)),{
va(vi("rddata_reg",t.offset),e.."_int_read");
va(e.."_lw_read_in_progress",0);
e.ackgen_code_pre={va(t.."_lw",t.."_lw_delay");
va(t.."_lw_delay",0);
vif(vand(vequal(vi("ack_sreg",1),1),vequal(t.."_lw_read_in_progress",1)),{
va(vi("rddata_reg",e.offset),t.."_int_read");
va(t.."_lw_read_in_progress",0);
});
};
t.extra_code={vcomment("asynchronous BIT register : "..t.name.." (type RW/WO, "..t.clock.." <-> clk_sys_i)");
vsyncprocess(t.clock,"rst_n_i",{
e.extra_code={vcomment("asynchronous BIT register : "..e.name.." (type RW/WO, "..e.clock.." <-> clk_sys_i)");
vsyncprocess(e.clock,"rst_n_i",{
vreset(0,{
va(e.."_lw_s0",0);
va(e.."_lw_s1",0);
va(e.."_lw_s2",0);
va(e.."_int_read",0);
va(e.."_load_o",0);
va(e.."_o",0);
va(t.."_lw_s0",0);
va(t.."_lw_s1",0);
va(t.."_lw_s2",0);
va(t.."_int_read",0);
va(t.."_load_o",0);
va(t.."_o",0);
});
vposedge({
va(e.."_lw_s0",e.."_lw");
va(e.."_lw_s1",e.."_lw_s0");
va(e.."_lw_s2",e.."_lw_s1");
vif(vand(vequal(e.."_lw_s2",0),vequal(e.."_lw_s1",1)),{
vif(vequal(e.."_rwsel",1),{
va(e.."_o",e.."_int_write");
va(e.."_load_o",1);
va(t.."_lw_s0",t.."_lw");
va(t.."_lw_s1",t.."_lw_s0");
va(t.."_lw_s2",t.."_lw_s1");
vif(vand(vequal(t.."_lw_s2",0),vequal(t.."_lw_s1",1)),{
vif(vequal(t.."_rwsel",1),{
va(t.."_o",t.."_int_write");
va(t.."_load_o",1);
},{
va(e.."_load_o",0);
va(e.."_int_read",e.."_i");
va(t.."_load_o",0);
va(t.."_int_read",t.."_i");
});
},{
va(e.."_load_o",0);
va(t.."_load_o",0);
});
});
});
};
elseif(t.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..t.name..")");
elseif(e.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..e.name..")");
end
end
end
......@@ -3252,6 +3186,8 @@ t.extra_code={va(e.."_o",vir("wrdata_reg",t));};
t.ackgen_code_pre={va(e.."_load_o",0);};
t.ackgen_code={va(e.."_load_o",0);};
t.reset_code_main={va(e.."_load_o",0);};
elseif(t.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..t.name..")");
end
else
if(t.access==ACC_RW_RO)then
......@@ -3610,7 +3546,7 @@ function wbgen_generate_eic()
if(periph.irqcount==0)then return;end
local t=0;
local s={};
local a={["__type"]=TYPE_REG;
local o={["__type"]=TYPE_REG;
["__blockindex"]=1e6;
["align"]=8;
["name"]="Interrupt disable register";
......@@ -3626,7 +3562,7 @@ signal(BIT,0,"eic_idr_write_int");};
["extra_code"]={va(vi("eic_idr_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));};
["no_std_regbank"]=true;
};
local o={["__type"]=TYPE_REG;
local a={["__type"]=TYPE_REG;
["__blockindex"]=1000001;
["align"]=1;
["name"]="Interrupt enable register";
......@@ -3678,7 +3614,7 @@ e.index=t;
t=t+1;
table.insert(s,{["index"]=e.index;["trigger"]=e.trigger;});
fix_prefix(e);
local t={
local s={
["__blockindex"]=e.index;
["__type"]=TYPE_FIELD;
["type"]=BIT;
......@@ -3689,7 +3625,7 @@ local t={
["access_bus"]=READ_WRITE;
["access_dev"]=READ_WRITE;
};
local s={
local t={
["__blockindex"]=e.index;
["__type"]=TYPE_FIELD;
["type"]=BIT;
......@@ -3731,16 +3667,16 @@ end
if(e.mask_line==true)then
table_join(e.ports,{port(BIT,0,"out",e.full_prefix.."_mask_o");});
end
table.insert(a,h);
table.insert(n,t);
table.insert(o,h);
table.insert(n,s);
table.insert(i,r);
table.insert(o,s);
table.insert(a,t);
end);
add_global_signals({
signal(SLV,periph.irqcount,"irq_inputs_vector_int");
});
table.insert(periph,a);
table.insert(periph,o);
table.insert(periph,a);
table.insert(periph,i);
table.insert(periph,n);
local e={vgm("g_num_interrupts",periph.irqcount);
......@@ -4145,14 +4081,14 @@ gen_pipelined_wb_signals(e);
foreach_reg(ALL_REG_TYPES,function(e)
gen_abstract_code(e);
end);
local o={};
local s={};
local n={};
local i={};
foreach_field(function(e,t)
table_join(o,e.reset_code_main);
table_join(s,e.reset_code_main);
end);
foreach_reg(ALL_REG_TYPES,function(e)
table_join(o,e.reset_code_main);
table_join(s,e.reset_code_main);
end);
foreach_reg({TYPE_REG},function(e)
foreach_subfield(e,function(e,t)
......@@ -4232,7 +4168,7 @@ vreset(0,{
va("ack_sreg",0);
va("ack_in_progress",0);
va("rddata_reg",0);
o
s
});
vposedge({
vcomment("advance the ACK generator shift register");
......@@ -4248,20 +4184,20 @@ e
};
if(periph.ramcount>0)then
if(not options.register_data_output)then
local a={"rddata_reg","rwaddr_reg"};
local t={};
local o={vswitch(vi("rwaddr_reg",address_bus_width-1,address_bus_width-address_bus_select_bits),t);};
local o={vcomment("Data output multiplexer process");vcombprocess(a,o);};
local t={"rddata_reg","rwaddr_reg"};
local a={};
local o={vswitch(vi("rwaddr_reg",address_bus_width-1,address_bus_width-address_bus_select_bits),a);};
local o={vcomment("Data output multiplexer process");vcombprocess(t,o);};
foreach_reg({TYPE_RAM},function(e)
table.insert(a,e.full_prefix.."_rddata_int");
local a={va(vi("wb_dat_o",e.width-1,0),e.full_prefix.."_rddata_int");};
table.insert(t,e.full_prefix.."_rddata_int");
local t={va(vi("wb_dat_o",e.width-1,0),e.full_prefix.."_rddata_int");};
if(e.width<DATA_BUS_WIDTH)then
table_join(a,{va(vi("wb_dat_o",DATA_BUS_WIDTH-1,e.width),0);});
table_join(t,{va(vi("wb_dat_o",DATA_BUS_WIDTH-1,e.width),0);});
end
table_join(t,{vcase(e.select_bits,a);});
table_join(a,{vcase(e.select_bits,t);});
end);
table.insert(a,"wb_adr_i");
table_join(t,{vcasedefault(va("wb_dat_o","rddata_reg"));});
table.insert(t,"wb_adr_i");
table_join(a,{vcasedefault(va("wb_dat_o","rddata_reg"));});
table_join(e,o);
end
local a={"wb_adr_i","rd_int","wr_int"};
......
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