White Rabbit Node Reference Design
The implementation of the WR-PTP protocol and appropriate network hardware is not a trivial task. The White Rabbit PTP Core (WRPC) was created to simplify the integration of the WR into both existing and embedded devices and systems. It is an HDL module that could be easily synthesized and used as a standalone WR interface inside a single FPGA chip or as an IP core in a larger design.
WRPC implements an IEEE1588 ordinary clock capable of reaching
sub-nanosecond accuracies and working both in Master and Slave modes. In
master mode the WRPC uses externally-provided reference time and
frequency to synchronize other WR compliant devices. When running in the
slave mode, WRPC receives the timing information from a PTP master,
synchronizes its internal clock and provides the timing information for
other IP cores through a simple VHDL interface.
Detailed description see G. Daniluk, T. Włostowski, White Rabbit:
sub-nanoseconds synchronization for embedded systems ,
PTTI 2011.
This page briefly describes the hardware requirements to integrate the WRPC into two projects: Upgrading an existing system with WRPC and building a compact embedded solution.
Upgrading an existing system
Only a few additional components are required to upgrade an existing system with the WRPC, presuming the existing project already includes an appropriate FPGA and the required environment (power supply, configuration etc.). WRPC has been successfully tested with GTP and GTX transceivers of Xilinx's FPGAs (e.g. Spartan-6 LXT family). Support for Altera GX PHYs is currently being implemented.
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The necessary external components are the fiber optic transceiver (SFP module) and two digitally tunable clock generators (one for the main PLL, one for producing the DMTD offset frequency). The remaining blocks outside the FPGA are optional and their use depends on the particular application: An optional I2C interface is provided for attaching an external EEPROM, which can store the device's configuration data (MAC address and calibration parameters).
The table below shows the FPGA utilization summary (PRELIMINARY) of the WRPC relevant resources only (Spartan-6, XC6SLX45T-3FGG484, ISE 13.4).
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More information
- Block diagram - PDF
file:
https://www.ohwr.org/project/white-rabbit/uploads/ee61c19ce89f5254fd93d8d530697997/FmcAdc250M12b2cha_Block_Diagram.pdf
- Schematic diagram - PDF
file:
https://www.ohwr.org/project/white-rabbit/uploads/db0141a3719d9853b66bf43ae9340f45/FmcAdc250M12b2cha_1_00_SCH.PDF
Building a compact embedded solution
This section describes the hardware of a standalone module which is a compact drop-in solution to achieve high-accuracy timing distribution with sub-ns synchronization based on WR.