White Rabbit Node Reference Design
The implementation of the WR-PTP protocol and appropriate network hardware is not a trivial task. The White Rabbit PTP Core (WRPC) was created to simplify the integration of the WR into both existing and embedded devices and systems. It is an HDL module that could be easily synthesized and used as a standalone WR interface inside a single FPGA chip or as an IP core in a larger design. The drawing below depicts the internal modules of the WRPC:
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Detailed description see:
G. Daniluk, T. Włostowski, White Rabbit: sub-nanoseconds
synchronization for embedded systems ,
PTTI 2011.
WRPC implements an IEEE1588 ordinary clock capable of reaching sub-nanosecond accuracies and working both in Master and Slave modes. In master mode the WRPC uses externally-provided reference time and frequency to synchronize other WR compliant devices. When running in the slave mode, WRPC receives the timing information from a PTP master, synchronizes its internal clock and provides the timing information for other IP cores through a simple VHDL interface.
This wiki page briefly describes the hardware requirements to integrate the WRPC into two projects: Upgrading an existing system with WRPC and building a compact embedded solution.
Upgrading an existing system
Only a few additional components are required to upgrade an existing system with the WRPC, presuming the existing project already includes an appropriate FPGA and the required environmental hardware (power supply, configuration etc.). WRPC has been successfully tested with GTP and GTX transceivers of Xilinx's FPGAs (e.g. Spartan-6 LXT family), support for Altera GX PHYs is currently being implemented.
The drawing below depicts the necessary external components to upgrade an existing system:
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The necessary external components are the fiber optic transceiver (SFP module) and two digitally tunable clock generators (one for the main PLL, one for producing the DMTD offset frequency). The remaining blocks outside the FPGA are optional and their use depends on the particular application: An optional I2C interface is provided for attaching an external EEPROM, which can store the device's configuration data (MAC address and calibration parameters).
The table below shows the FPGA utilization summary (PRELIMINARY) of the WRPC relevant resources only (Spartan-6, XC6SLX45T-3FGG484, ISE 13.4):
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More information
- Schematic diagram - PDF
file:
https://www.ohwr.org/project/white-rabbit/uploads/8add23567c3dff7030126d7568e08a41/WRPC_upgrade_existing_schematic.pdf
- Altium (summer '09) project
file:
https://www.ohwr.org/project/white-rabbit/uploads/9673e4f6f6013af77591200321a9fbe3/WRPC_upgrade_existing_altium.zip
Building a compact embedded solution
As soon as possible we will present here the hardware for a compact standalone module usable as a drop-in solution to achieve high-accuracy timing distribution with sub-ns synchronization based on WR.
Scheduled features may include:
- Compact size, formfactor TBD
- Based on Xilinx XC6SLX25T (CSG324)
- Single supply operation (e.g. +12 V input, DC/DC converters onboard)
- Inputs / outputs for PPS and external frequency
- FLASH configuration memory
- Master / slave operation selectable by jumper (multiboot)
- MAC address allocation TBD
Contacts
- Daniel Florin - Physik Institut, Universitaet Zuerich
- Achim Vollhardt - Physik Institut, Universitaet Zuerich
Useful references
- White Rabbit
- Compliant SFP types
- Building WR PTP Core
- White Rabbit Core Collection
- White Rabbit Software for PTP Core
Daniel Florin - 08 May 2012