A quick explanation on the internals of the MCH Main FPGA

The main FPGA is a Cyclone 3 from Altera. It is interfaced to the Main CPU as a memory mapped peripheral, i.e. between the main CPU and this FPGA there is an address bus, a data bus, some chip selects and some IRQ lines. Its interface with the watchdog CPU is an SPI bus, and it's also connected to the timing FPGA through another SPI bus and some user lines. The fact that the interconnect between the two FPGAs is SPI is of course a matter of configuration.

There are three main components in this FPGA:

• The WR end point. This is an Ethernet MAC with precise time-stamping and buffering. There is only one of them in the current design, but there should soon be 10: 8 for downlinks and 2 for uplinks.
• The NIC. This is the part of the FPGA which services packets going from and to the local Switch MAC address. Its name comes from the fact that it acts as a Network Interface Card of the main CPU, i.e. every time a packet is sent to the switch with that destination MAC address, the NIC interrupts the main CPU and the CPU then goes, reads the packet and feeds it to its network stack in the Linux kernel. Sending packets from the main CPU also happens through the NIC.
• The interconnect. This is rather undefined up to now, but a very critical part of the design. Current thinking involves a multi-port memory and some kind of round-robin mechanism with a notion of priority. A little dedicated processor with microcode is not excluded.

The main FPGA will use an external ZBT memory to store MAC address tables. The exact mechanism and data structures are not defined yet.

JavierSerrano - 23 Nov 2009