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docs/specs/HDL: copy hdlspecs from old svn repo

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/*
-------------------------------------------------------------------------------
-- Title : Routing Table Unit Software Simulation
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : rtu_sim.c
-- Authors : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-27
-- Last update: 2010-06-30
-- Description: - functions necessary to fill in tables representing H/W memories
-- - simulation engine
--
--
-- Revisions :
-- Date Version Author Description
-- 2010-04-27 1.0 twlostow Created
-- 2010-06-30 1.1 Maciej Lipinski changes to algorithm, functions to input
data to data structures
*/
#include <stdio.h>
#include "rtu_sim.h"
#include "rtu_test_main.h"
int rtu_sim_read_hcam_entry( uint16_t i)
{
int hcam_active_bank = (CFG.cam_bank == 0 ? 1 : 0);
printf("sim_hcam[bank = %d][addr = 0x%x]: mac: 0x%2x%2x%2x%2x%2x%2x , fid: 0x%x\n",hcam_active_bank , i,rtu_cam[hcam_active_bank][i].mac[0],rtu_cam[hcam_active_bank][i].mac[1],rtu_cam[hcam_active_bank][i].mac[2],rtu_cam[hcam_active_bank][i].mac[3],rtu_cam[hcam_active_bank][i].mac[4],rtu_cam[hcam_active_bank][i].mac[5],rtu_cam[hcam_active_bank][i].fid) ;
}
/*
set active ZBT bank (0 or 1)
*/
int rtu_sim_set_active_htab_bank(uint8_t bank)
{
if(bank != 0 && bank != 1)
return -1;
CFG.rtu_bank = bank;
return 1;
}
/*
set active CAM bank (0 or 1)
*/
int rtu_sim_set_active_hcam_bank(uint8_t bank)
{
if(bank != 0 && bank != 1)
return -1;
CFG.cam_bank = bank;
return 1;
}
/*
setting:
# FIX_PRIO [read/write]: Fix priority
1: Port has fixed priority of value PRIO_VAL. It overrides the priority coming from the endpoint
0: Use priority from the endpoint
# PRIO_VAL [read/write]: Priority value
Fixed priority value for the port. Used instead the endpoint-assigned priority when FIX_PRIO = 1
*/
int rtu_sim_set_fixed_prio_on_port(int port, uint8_t prio, uint8_t set)
{
if(set)
{
CFG.port_cfg[port].fixed_prio_ena = 1;
CFG.port_cfg[port].fixed_prio_val = prio;
}
else
{
CFG.port_cfg[port].fixed_prio_ena = 0;
CFG.port_cfg[port].fixed_prio_val = 0;
}
}
/*
Set basic RTU configuration
* HT_BSEL [read/write]: Main table bank select
Selects active bank of RTU hashtable (ZBT).
0: bank 0 is used by lookup engine and bank 1 can be accessed using MFIFO
1: bank 1 is used by lookup engine and bank 0 can be accessed using MFIFO
* HCAM_BSEL [read/write]: Hash collision table (HCAM) bank select
Selects active bank of RTU extra memory for colliding hashes.
0: bank 0 is used by lookup engine
1: bank 1 is used by lookup engine
* G_ENA [read/write]: RTU Global Enable
Global RTU enable bit. Overrides all port settings.
0: RTU is disabled. All packets are dropped.
1: RTU is enabled.
*/
int rtu_sim_rtu_setting(uint8_t global_enable,uint8_t hcam_bank,uint8_t htab_bank, uint32_t hash_poly)
{
CFG.global_enable = global_enable;
CFG.cam_bank = (int) hcam_bank;
CFG.rtu_bank = (int) htab_bank;
CFG.hash_poly = hash_poly;
}
int rtu_sim_set_hash_poly(uint32_t hash_poly)
{
CFG.hash_poly = hash_poly;
}
/*
Set basic RTU configuration
for a given port, possible settings:
* LEARN_EN [read/write]: Learning enable
1: enables learning process on this port. Unrecognized requests will be put into UFIFO
0: disables learning. Unrecognized requests will be either broadcast or dropped.
* PASS_ALL [read/write]: Pass all packets
1: all packets are passed (depending on the rules in RT table).
0: all packets are dropped on this port.
* PASS_BPDU [read/write]: Pass BPDUs
1: BPDU packets (with dst MAC 01:80:c2:00:00:00) are passed according to RT rules. This setting overrides PASS_ALL.
0: BPDU packets are dropped.
* FIX_PRIO [read/write]: Fix priority
1: Port has fixed priority of value PRIO_VAL. It overrides the priority coming from the endpoint
0: Use priority from the endpoint
* PRIO_VAL [read/write]: Priority value
Fixed priority value for the port. Used instead the endpoint-assigned priority when FIX_PRIO = 1
* B_UNREC [read/write]: Unrecognized request behaviour
Sets the port behaviour for all unrecognized requests:
0: packet is dropped
1: packet is broadcast
*/
int rtu_sim_rtu_port_setting(int port, uint32_t settings)
{
if(settings & FPGA_RTU_PCR_LEARN_EN)
CFG.port_cfg[port].learning_enabled = 1;
else
CFG.port_cfg[port].learning_enabled = 0;
if(settings & FPGA_RTU_PCR_PASS_ALL)
CFG.port_cfg[port].pass_all = 1;
else
CFG.port_cfg[port].pass_all = 0;
if(settings & FPGA_RTU_PCR_PASS_BPDU)
CFG.port_cfg[port].forward_bpdu_only = 1;
else
CFG.port_cfg[port].forward_bpdu_only = 0;
if(settings & FPGA_RTU_PCR_B_UNREC)
CFG.port_cfg[port].b_unrec = 1;
else
CFG.port_cfg[port].b_unrec = 0;
if(settings & FPGA_RTU_PCR_FIX_PRIO)
{
CFG.port_cfg[port].fixed_prio_ena = 1;
CFG.port_cfg[port].fixed_prio_val = 0x7 & (settings >> 4);
}
else
{
CFG.port_cfg[port].fixed_prio_ena = 0;
CFG.port_cfg[port].fixed_prio_val = 0;
}
return 1;
}
/*
basic settings
*/
int rtu_sim_set()
{
// enable learning on all ports
int i;
for(i=0;i<RTU_NUM_PORTS;i++)
{
CFG.port_cfg[i].learning_enabled = 1;
CFG.port_cfg[i].forward_bpdu_only = 0;
}
CFG.cam_bank = 0;
CFG.rtu_bank = 0;
return 1;
}
int rtu_sim_read_global_setting()
{
int i;
printf("Reading RTU Global setting:\n");
if( CFG.global_enable)
printf("RTU enabled; ");
else
printf("RTU disabled; ");
if(CFG.cam_bank)
printf("hcam_bank = 1; ");
else
printf("hcam_bank = 0; ");
if(CFG.rtu_bank)
printf("htab_bank = 1; ");
else
printf("htab_bank = 0; ");
printf("poly= 0x%x\n",CFG.hash_poly);
}
/*
Writes entry to a table representing zbt sram in software.
*/
int rtu_sim_write_htab_entry(int valid, int end_of_bucket, int is_bpdu, int go_to_cam , \
uint8_t fid, uint16_t mac_hi, uint32_t mac_lo, \
uint8_t cam_addr, int drop_when_source, int drop_when_dest, int drop_when_unmatched_src_ports, \
uint8_t prio_src, uint8_t has_prio_src, uint8_t prio_override_src, \
uint8_t prio_dst, int has_prio_dst, int prio_override_dst, \
uint16_t port_mask_src, uint16_t port_mask_dst, uint32_t last_access , uint32_t zbt_addr /*, int bank */, int bucket)
{
int addr = zbt_addr >> 5;
int bank;
if(CFG.rtu_bank == 1 ) bank = 0;
else if(CFG.rtu_bank == 0 ) bank = 1;
else {printf("ERROR\n"); return -1;}
#ifdef ML_DBG
printf("writing data to zbt: bank = %d, htab_addr = 0x%3x [zbt_addr = 0x%3x], bucket = %d\n", bank,addr,zbt_addr,bucket);
#endif
rtu_tab[bank].buckets[addr][bucket].valid = valid;
rtu_tab[bank].buckets[addr][bucket].end_of_bucket = end_of_bucket;
rtu_tab[bank].buckets[addr][bucket].is_bpdu = is_bpdu;
rtu_tab[bank].buckets[addr][bucket].mac[0] = (mac_hi >> 8);
rtu_tab[bank].buckets[addr][bucket].mac[1] = (0xFF & mac_hi);
rtu_tab[bank].buckets[addr][bucket].mac[2] = (0xFF & (mac_lo >> 24));
rtu_tab[bank].buckets[addr][bucket].mac[3] = (0xFF & (mac_lo >> 16));
rtu_tab[bank].buckets[addr][bucket].mac[4] = (0xFF & (mac_lo >> 8));
rtu_tab[bank].buckets[addr][bucket].mac[5] = (0xFF & mac_lo) ;
rtu_tab[bank].buckets[addr][bucket].fid = fid;
rtu_tab[bank].buckets[addr][bucket].port_mask_src = port_mask_src;
rtu_tab[bank].buckets[addr][bucket].port_mask_dst = port_mask_dst;
rtu_tab[bank].buckets[addr][bucket].drop_when_source = drop_when_source;
rtu_tab[bank].buckets[addr][bucket].drop_when_dest = drop_when_dest;
rtu_tab[bank].buckets[addr][bucket].drop_unmatched_src_ports = drop_when_unmatched_src_ports;
rtu_tab[bank].buckets[addr][bucket].last_access_t = last_access;
rtu_tab[bank].buckets[addr][bucket].prio_src = prio_src;
rtu_tab[bank].buckets[addr][bucket].has_prio_src = has_prio_src;
rtu_tab[bank].buckets[addr][bucket].prio_override_src = prio_override_src;
rtu_tab[bank].buckets[addr][bucket].prio_dst = prio_dst;
rtu_tab[bank].buckets[addr][bucket].has_prio_dst = has_prio_dst;
rtu_tab[bank].buckets[addr][bucket].prio_override_dst = prio_override_dst;
rtu_tab[bank].buckets[addr][bucket].go_to_cam = go_to_cam;
rtu_tab[bank].buckets[addr][bucket].cam_addr = cam_addr;
return 1;
}
/*
Writes entry to a table representing hcam in software.
*/
int rtu_sim_write_hcam_entry(int valid, int end_of_bucket, int is_bpdu, int go_to_cam , \
uint8_t fid, uint16_t mac_hi, uint32_t mac_lo, \
uint8_t cam_addr, int drop_when_source, int drop_when_dest, int drop_when_unmatched_src_ports, \
uint8_t prio_src, uint8_t has_prio_src, uint8_t prio_override_src, \
uint8_t prio_dst, int has_prio_dst, int prio_override_dst, \
uint16_t port_mask_src, uint16_t port_mask_dst, uint32_t last_access , uint16_t hcam_addr /*, int bank */)
{
int addr = hcam_addr/8;
int bank;
if(CFG.cam_bank == 1 ) bank = 0;
else if(CFG.cam_bank == 0 ) bank = 1;
else {printf("ERROR\n"); return -1;}
#ifdef ML_DBG
printf("writing data to cam: bank = %d, entry number = %d [hcam_addr = 0x%x]\n", bank,addr,hcam_addr);
#endif
rtu_cam[bank][addr].valid = valid;
rtu_cam[bank][addr].end_of_bucket = end_of_bucket;
rtu_cam[bank][addr].is_bpdu = is_bpdu;
rtu_cam[bank][addr].mac[0] = (mac_hi >> 8);
rtu_cam[bank][addr].mac[1] = (0xFF & mac_hi);
rtu_cam[bank][addr].mac[2] = (0xFF & (mac_lo >> 24));
rtu_cam[bank][addr].mac[3] = (0xFF & (mac_lo >> 16));
rtu_cam[bank][addr].mac[4] = (0xFF & (mac_lo >> 8));
rtu_cam[bank][addr].mac[5] = (0xFF & mac_lo) ;
rtu_cam[bank][addr].fid = fid;
rtu_cam[bank][addr].port_mask_src = port_mask_src;
rtu_cam[bank][addr].port_mask_dst = port_mask_dst;
rtu_cam[bank][addr].drop_when_source = drop_when_source;
rtu_cam[bank][addr].drop_when_dest = drop_when_dest;
rtu_cam[bank][addr].drop_unmatched_src_ports = drop_when_unmatched_src_ports;
rtu_cam[bank][addr].last_access_t = last_access;
rtu_cam[bank][addr].prio_src = prio_src;
rtu_cam[bank][addr].has_prio_src = has_prio_src;
rtu_cam[bank][addr].prio_override_src = prio_override_src;
rtu_cam[bank][addr].prio_dst = prio_dst;
rtu_cam[bank][addr].has_prio_dst = has_prio_dst;
rtu_cam[bank][addr].prio_override_dst = prio_override_dst;
rtu_cam[bank][addr].go_to_cam = go_to_cam;
rtu_cam[bank][addr].cam_addr = cam_addr;
return 1;
}
/*
Writes entry to a table representing vlan in software.
*/
int rtu_sim_write_vlan_entry(int addr, uint32_t port_mask,uint8_t fid,uint8_t prio,int has_prio,int prio_override,int drop)
{
#ifdef ML_DBG
printf("writing data to vlan: addr = 0x%x]\n", addr);
#endif
vlan_tab[addr].port_mask = port_mask;
vlan_tab[addr].fid = fid;
vlan_tab[addr].prio = prio;
vlan_tab[addr].has_prio = has_prio;
vlan_tab[addr].prio_override = prio_override;
vlan_tab[addr].drop = drop;
return 1;
}
int rtu_sim_read_arg_htab_changes(changed_aging_htab_word_t sim_agr_htab[])
{
int i;
int sim_cnt;
uint32_t tmp;
// remembering changed words from agr_htab memory in simulation
sim_cnt=0;
for(i=0;i<256;i++)
{
if(rtu_agr_htab[i] != 0x00000000)
{
//fprintf(stderr, "agr_htab[0x%x] = 0x%8x\n",i,rtu_agr_htab[i]);
sim_agr_htab[sim_cnt].address = i;
sim_agr_htab[sim_cnt].word = rtu_agr_htab[i];
sim_cnt++;
}
}
return sim_cnt;
}
//////////////////////////////////// cleaning mems ////////////////////////////////////
/*
Cleans tables repesenting H/W memories (zbt sram, vlan, hcam,
*/
int rtu_sim_clean_mems()
{
int i, j;
for(i=0;i<RTU_ENTRIES/RTU_BUCKETS;i++)
for(j=0;j<RTU_BUCKETS;j++)
{
rtu_tab[0].buckets[i][j].valid = 0;
rtu_tab[0].buckets[i][j].end_of_bucket = 0;
rtu_tab[0].buckets[i][j].is_bpdu = 0;
rtu_tab[0].buckets[i][j].mac[0] = 0;
rtu_tab[0].buckets[i][j].mac[1] = 0;
rtu_tab[0].buckets[i][j].mac[2] = 0;
rtu_tab[0].buckets[i][j].mac[3] = 0;
rtu_tab[0].buckets[i][j].mac[4] = 0;
rtu_tab[0].buckets[i][j].mac[5] = 0;
rtu_tab[0].buckets[i][j].fid = 0;
rtu_tab[0].buckets[i][j].port_mask_src = 0;
rtu_tab[0].buckets[i][j].port_mask_dst = 0;
rtu_tab[0].buckets[i][j].drop_when_source = 0;
rtu_tab[0].buckets[i][j].drop_when_dest = 0;
rtu_tab[0].buckets[i][j].drop_unmatched_src_ports = 0;
rtu_tab[0].buckets[i][j].last_access_t = 0;
rtu_tab[0].buckets[i][j].prio_src = 0;
rtu_tab[0].buckets[i][j].has_prio_src = 0;
rtu_tab[0].buckets[i][j].prio_override_src = 0;
rtu_tab[0].buckets[i][j].prio_dst = 0;
rtu_tab[0].buckets[i][j].has_prio_dst = 0;
rtu_tab[0].buckets[i][j].prio_override_dst = 0;
rtu_tab[0].buckets[i][j].go_to_cam = 0;
rtu_tab[0].buckets[i][j].cam_addr = 0 ;
rtu_tab[1].buckets[i][j].valid = 0;
rtu_tab[1].buckets[i][j].valid = 0;
rtu_tab[1].buckets[i][j].end_of_bucket = 0;
rtu_tab[1].buckets[i][j].is_bpdu = 0;
rtu_tab[1].buckets[i][j].mac[0] = 0;
rtu_tab[1].buckets[i][j].mac[1] = 0;
rtu_tab[1].buckets[i][j].mac[2] = 0;
rtu_tab[1].buckets[i][j].mac[3] = 0;
rtu_tab[1].buckets[i][j].mac[4] = 0;
rtu_tab[1].buckets[i][j].mac[5] = 0;
rtu_tab[1].buckets[i][j].fid = 0;
rtu_tab[1].buckets[i][j].port_mask_src = 0;
rtu_tab[1].buckets[i][j].port_mask_dst = 0;
rtu_tab[1].buckets[i][j].drop_when_source = 0;
rtu_tab[1].buckets[i][j].drop_when_dest = 0;
rtu_tab[1].buckets[i][j].drop_unmatched_src_ports = 0;
rtu_tab[1].buckets[i][j].last_access_t = 0;
rtu_tab[1].buckets[i][j].prio_src = 0;
rtu_tab[1].buckets[i][j].has_prio_src = 0;
rtu_tab[1].buckets[i][j].prio_override_src = 0;
rtu_tab[1].buckets[i][j].prio_dst = 0;
rtu_tab[1].buckets[i][j].has_prio_dst = 0;
rtu_tab[1].buckets[i][j].prio_override_dst = 0;
rtu_tab[1].buckets[i][j].go_to_cam = 0;
rtu_tab[1].buckets[i][j].cam_addr = 0;
//rtu_tab[1].buckets[i][j].valid = 0;
}
for(i=0;i<CAM_ENTRIES;i++)
{
// rtu_cam[0][i].valid = 0;
// rtu_cam[1][i].valid = 0;
rtu_cam[0][i].valid = 0;
rtu_cam[0][i].end_of_bucket = 0;
rtu_cam[0][i].is_bpdu = 0;
rtu_cam[0][i].mac[0] = 0;
rtu_cam[0][i].mac[1] = 0;
rtu_cam[0][i].mac[2] = 0;
rtu_cam[0][i].mac[3] = 0;
rtu_cam[0][i].mac[4] = 0;
rtu_cam[0][i].mac[5] = 0;
rtu_cam[0][i].fid = 0;
rtu_cam[0][i].port_mask_src = 0;
rtu_cam[0][i].port_mask_dst = 0;
rtu_cam[0][i].drop_when_source = 0;
rtu_cam[0][i].drop_when_dest = 0;
rtu_cam[0][i].drop_unmatched_src_ports = 0;
rtu_cam[0][i].last_access_t = 0;
rtu_cam[0][i].prio_src = 0;
rtu_cam[0][i].has_prio_src = 0;
rtu_cam[0][i].prio_override_src = 0;
rtu_cam[0][i].prio_dst = 0;
rtu_cam[0][i].has_prio_dst = 0;
rtu_cam[0][i].prio_override_dst = 0;
rtu_cam[0][i].go_to_cam = 0;
rtu_cam[0][i].cam_addr = 0 ;
rtu_cam[1][i].valid = 0;
rtu_cam[1][i].end_of_bucket = 0;
rtu_cam[1][i].is_bpdu = 0;
rtu_cam[1][i].mac[0] = 0;
rtu_cam[1][i].mac[1] = 0;
rtu_cam[1][i].mac[2] = 0;
rtu_cam[1][i].mac[3] = 0;
rtu_cam[1][i].mac[4] = 0;
rtu_cam[1][i].mac[5] = 0;
rtu_cam[1][i].fid = 0;
rtu_cam[1][i].port_mask_src = 0;
rtu_cam[1][i].port_mask_dst = 0;
rtu_cam[1][i].drop_when_source = 0;
rtu_cam[1][i].drop_when_dest = 0;
rtu_cam[1][i].drop_unmatched_src_ports = 0;
rtu_cam[1][i].last_access_t = 0;
rtu_cam[1][i].prio_src = 0;
rtu_cam[1][i].has_prio_src = 0;
rtu_cam[1][i].prio_override_src = 0;
rtu_cam[1][i].prio_dst = 0;
rtu_cam[1][i].has_prio_dst = 0;
rtu_cam[1][i].prio_override_dst = 0;
rtu_cam[1][i].go_to_cam = 0;
rtu_cam[1][i].cam_addr = 0 ;
}
learning_queue.head = 0;
learning_queue.tail = MAX_FIFO_SIZE-1;
learning_queue.count = 0;
// by default, VLANs are disabled
for(i=1;i<MAX_VLANS;i++)
{
vlan_tab[i].drop = 1;
}
// clean main aging memory
for(i=0;i< ARAM_WORDS; i++)
rtu_agr_htab[i]= 0x00000000;
//clean hcam aging reg
rtu_agr_hcam= 0x00000000;
return 1;
}
char * mac_2_string(mac_addr_t mac)
{
char str[80];
sprintf(str, "%02x:%02x:%02x:%02x:%02x:%02x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
return strdup(str);
}
int cmp_macs(mac_addr_t mac_1,mac_addr_t mac_2)
{
int i;
for (i=0;i<6;i++)
if(mac_1[i]!=mac_2[i]) return 0;
return 1;
}
/******************************************************************************/
/* FUNCTIONS BELOW CONTAIN THE RTU ALGORITHM TO BE IMPLEMENTED IN VHDL */
/******************************************************************************/
/* CHANGES TO THE ALGORITHM BY maciej.lipinski@cern.ch
- if message dropped, port_mask and prio are set to 0x0
- request is sent to learning queue only once during match,
initially, if the source entry was not found, the request was sent to
learning queue, subsequently if the destinatin entry was not found as well,
the (same) request was sent to learning queue again
*/
/******************************************************************************/
void add_to_learning_queue(rtu_request_t rq, int verbose)
{
if(verbose) printf("add_to_learning_queue: src=%s dst=%s vid=%d port=%d prio_has=%d prio=%d\n", mac_2_string(rq.src), mac_2_string(rq.dst), rq.has_vid?rq.vid:0, rq.port_id,rq.has_prio, rq.prio);
if(learning_queue.count == MAX_FIFO_SIZE) // Learning FIFO is full? - drop the request.
return;
learning_queue.count++;
learning_queue.head++;
if(learning_queue.head == MAX_FIFO_SIZE) learning_queue.head = 0;
learning_queue.data[learning_queue.head] = rq;
}
// hash function - use your invention here, it doesn't need to use CRC
// mac - mac address, fid = Filtering Database ID
uint16_t hash_function(mac_addr_t mac, uint8_t fid)
{
uint16_t ret_hash ;
uint16_t mac_hi = (uint16_t)((mac[0] << 8) | mac[1]);
uint32_t mac_lo = (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
ret_hash = hash(mac_hi, mac_lo, fid);
/*
// needed to change here to my functions which is
// synchronized with VHDL CRC
hash = crc16(hash, (0xFFFF & vlan));
hash = crc16(hash, ((uint16_t)mac[0] << 8) | mac[1]);
hash = crc16(hash, ((uint16_t)mac[2] << 8) | mac[3]);
hash = crc16(hash, ((uint16_t)mac[4] << 8) | mac[5]);
*/
return ret_hash & 0xfff; //clip it to the MAC table size
}
int mac_table_lookup(mac_addr_t mac, uint8_t fid, mac_table_entry_t **found,int verbose)
{
// 1st step: calculate hash of MAC + FID pair
uint16_t hash = hash_function(mac, fid);
mac_table_entry_t *ent;
int i;
char str[80];
sprintf(str, "%02x:%02x:%02x:%02x:%02x:%02x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
if(verbose) printf("hash [fid=0x%x mac=%s] = 0x%x bank = %d\n",fid, str, hash,CFG.rtu_bank);
// get the entry with matching hash in MAC table
ent = rtu_tab[CFG.rtu_bank].buckets[hash];
// 2nd step: scan the bucket array for matching MAC+FID pair
for(i =0; i<RTU_BUCKETS && ent->valid;i++,ent++)
{
//printf("\tlooking for: mac=%s fid=0x%x ,have: mac=%02x:%02x:%02x:%02x:%02x:%02x fid=0x%x [addr=0x%x], bucket = %d\n\n",str,fid,ent->mac[0], ent->mac[1], ent->mac[2], ent->mac[3], ent->mac[4], ent->mac[5],ent->fid,hash,i);
//if(ent->mac == mac && ent->fid == fid) // found matching rule in the current bucket?
if(cmp_macs(ent->mac, mac)==1 && ent->fid == fid) // found matching rule in the current bucket?
{
#ifdef ML_DBG
printf("\t----------------------\n");
printf("\nBINGO,entry found in htab for addr=0x%x, bucket = %d\n\n",hash,i);
printf("\trtu_agr_htab[0x%x] = 0x%8x\n",(hash >> 3),0x1 << (((0x7 & hash) << 2) | (0x3 & i)));
printf("\t----------------------\n");
#endif
if(verbose) printf("> found in htab, bucket=%d <\n",i);
number_of_found_entries++;
//added by ML
if(verbose) printf("\n\nbefore: 0x%x , hash=0x%x, i=%i\n",rtu_agr_htab[(hash >> 3)],hash,i);
//if(verbose) printf("\n\nrtu_agr_htab[(hash >> 3)]= ( 0x1 << (((0x7 & hash) << 2) | (0x00000003 & (unsigned int)i) )) | rtu_agr_htab[(hash >> 3)] \n");
//if(verbose) printf("\n\n 0x%8x = 1 << (0x%8x | 0x%8x ) | 0x%8x \n", \
( 0x1 << (((0x7 & hash) << 2) | (0x00000003 & (unsigned int)i)) ) | rtu_agr_htab[(hash >> 3)], \
0x1 << ((0x7 & hash) << 2) , \
(0x00000003 & (unsigned int)i) , \
rtu_agr_htab[(hash >> 3)]);
rtu_agr_htab[(hash >> 3)]= ( 0x1 << (((0x7 & hash) << 2) | (0x00000003 & (unsigned int)i)) ) | rtu_agr_htab[(hash >> 3)];
if(verbose) printf("after: 0x%x \n\n",rtu_agr_htab[(hash >> 3)]);
/////
*found = ent;
return 1;
} else if (ent->go_to_cam) // the bucket is bigger than RTU_BUCKETS entries - go find the matching one in CAM memory.
{
// printf("go to cam, cam_addr: 0x%x \n",ent->cam_addr);
int j = ent->cam_addr; // cam_addr in the last entry in the bucket points to the location of the next rule in CAM memory
// 3rd step: traverse the CAM memory until we find a matching entry or reach end of the bucket
for(; j<CAM_ENTRIES /*ML: && !rtu_cam[CFG.cam_bank][j].end_of_bucket */; j++)
{
#ifdef ML_DBG
printf("[addr = 0x%x]looking in hcam foe: mac=%s fid=0x%x ,have: mac=%02x:%02x:%02x:%02x:%02x:%02x fid=0x%x [addr=0x%x],end=%d \n\n",j,str,fid,rtu_cam[CFG.cam_bank][j].mac[0], rtu_cam[CFG.cam_bank][j].mac[1], rtu_cam[CFG.cam_bank][j].mac[2], rtu_cam[CFG.cam_bank][j].mac[3], rtu_cam[CFG.cam_bank][j].mac[4], rtu_cam[CFG.cam_bank][j].mac[5],rtu_cam[CFG.cam_bank][j].fid,j,rtu_cam[CFG.cam_bank][j].end_of_bucket);
#endif
if( cmp_macs(rtu_cam[CFG.cam_bank][j].mac, mac) == 1 && rtu_cam[CFG.cam_bank][j].fid == fid)
{
#ifdef ML_DBG
printf("\t----------------------\n");
printf("\nBINGO,entry foundin hcam for addr=0x%x, bucket = %d\n\n",hash,j);
printf("\trtu_agr_hcam] = 0x%8x\n",(0x1 << j));
printf("\t----------------------\n");
#endif
if(verbose) printf("> found in hcam <\n");
number_of_found_entries++;
*found = &rtu_cam[CFG.cam_bank][j]; // found matching entry in CAM
if(verbose) printf("\n\nbefore: 0x%x , hash=0x%x, i=%i\n",rtu_agr_hcam,hash,i);
rtu_agr_hcam = (0x1 << j) | rtu_agr_hcam;
if(verbose) printf("after: 0x%x \n\n",rtu_agr_hcam);
return 1;
}
else if(rtu_cam[CFG.cam_bank][j].end_of_bucket == 1)
break; //end if the bucket, nothing found
}
}
}
// not found (neither in MAC table nor in CAM): return 0
return 0;
}
#define PRIO_SOURCE 0
#define PRIO_DESTINATION 1
#define PRIO_VID 2
#define PRIO_PORT 3
#define NOT_DEFINED -1
// main rtu function: decides what to do with packet "rq"
int rtu_sim_match(rtu_request_t rq, rtu_response_t *rsp, int verbose )
{
//added by ML:
int already_in_learning_queue = 0;
///////////
if(verbose) printf("rtu_match: src=%s dst=%s vid=0x%x port=%d port_prio=%d , has_prio = 0x%x, has_vid = 0x%x\n", mac_2_string(rq.src), mac_2_string(rq.dst), rq.has_vid?rq.vid:0, rq.port_id, rq.prio,rq.has_prio,rq.has_vid);
rsp->port_id = rq.port_id;
//added by ML
if(CFG.global_enable == 0)
{
if(verbose) printf("rtu_match: dropped (RTU disabled)\n");
rsp->drop = 1;
rsp->prio = 0;
rsp->port_mask = 0;
return 0;
}
//ML: pass_all is in general port_enable,
// port disabling by setting pass_all=0 can be overriden by setting forward_bpdu_only=1
// so, regardless of pass_all's value, forward_bpdu_only causes only bpdu packages to be
// passed through
if(CFG.port_cfg[rq.port_id].pass_all == 0 && CFG.port_cfg[rq.port_id].forward_bpdu_only == 0)
{
if(verbose) printf("rtu_match: dropped (port %d disabled)\n",rq.port_id);
rsp->drop = 1;
rsp->prio = 0;
rsp->port_mask = 0;
return 0;
}
/*
implementing it this way, results in the fact that the changed
priority is learned
*/
// check if packet has per-port assigned priority
if(CFG.port_cfg[rq.port_id].fixed_prio_ena)
{
rq.prio = CFG.port_cfg[rq.port_id].fixed_prio_val;
rq.has_prio = 0x1;
if(verbose) printf("setting to fixed prio(new data): has_prio = %d, prio = %d\n",CFG.port_cfg[rq.port_id].fixed_prio_ena, CFG.port_cfg[rq.port_id].fixed_prio_val);
}
/////////////
// helper tables for priority selection.
// priority from the most specific to least specific definitions (e.g, per tag -> per source MAC -> per destination MAC -> per VLAN )
int prio_lookup[4] = {NOT_DEFINED, NOT_DEFINED, NOT_DEFINED, NOT_DEFINED};
int prio_override[4] = {0,0,0,0};
vlan_table_entry_t vent;
//////////////////////////////////////////////////////////////////////////////
// 1st step: determine the VLAN table entry for the packet VID
//////////////////////////////////////////////////////////////////////////////
uint16_t vid = (rq.has_vid ? rq.vid : 0); // if the packet has the VLAN id, use it, otherwise - use VID for untagged packets (0)
vent = vlan_tab[vid];
if(vent.drop) // VLAN is illegal - drop the packet and return
{
if(verbose) printf("rtu_match: dropped (blocked VLAN)\n");
rsp->drop = 1;
//added by ML
rsp->prio = 0;
rsp->port_mask = 0;
/////////////
return 0;
}
if(vent.has_prio) // VLAN has defined priority - add it to priority selection table
{
prio_lookup[PRIO_VID] = vent.prio;
prio_override[PRIO_VID] = vent.prio_override;
}
////////////////////////////////////////////////
// 2nd step: find the source MAC in MAC table
/////////////////////////////////////////////////
mac_table_entry_t *entry_src;
uint32_t port_mask_src;
int drop_unmatched_src_ports;
if(mac_table_lookup(rq.src, vent.fid, &entry_src,verbose)) // lookup the source MAC address in the table
{ // found:
port_mask_src = entry_src->port_mask_src;
if(entry_src->drop_when_source) // source MAC address is blocked? - drop the packet
{
if(verbose) printf("rtu_match: dropped (blocked source MAC)\n");
//added by ML
rsp->prio = 0;
rsp->port_mask = 0;
/////////////
rsp->drop = 1;
return 0;
}
if(entry_src->has_prio_src) // check if the source MAC has predefined priority and eventually add it to the selection table
{
prio_lookup[PRIO_SOURCE] = entry_src->prio_src;
prio_override[PRIO_SOURCE] = entry_src->prio_override_src;;
}
drop_unmatched_src_ports = entry_src->drop_unmatched_src_ports;
} else { // source MAC not found: assume it can come from any port, put the entry into learning queue
port_mask_src = 0xffffffff;
drop_unmatched_src_ports = 0;
if(CFG.port_cfg[rq.port_id].learning_enabled && (already_in_learning_queue==0))
{
add_to_learning_queue(rq,verbose);
already_in_learning_queue = 1;
}
}
// check if the packet with given source MAC can come from this port.
if(! ((1<<rq.port_id) & port_mask_src))
{
if(drop_unmatched_src_ports) { // if the MAC address is locked to source port, drop the paket
if(verbose) printf("rtu_match: dropped (source MAC doesn't match source port)\n");
//added by ML
rsp->prio = 0;
rsp->port_mask = 0;
/////////////
rsp->drop =1;
return 0;
} else { // otherwise add it to the learning queue - perhaps device has been reconnected to another port and topology info needs to be updated
if(CFG.port_cfg[rq.port_id].learning_enabled && (already_in_learning_queue==0))
{
if(verbose) printf("\n-----------------------\n");
if(verbose) printf("we have problem here???\n");
if(verbose) printf("(1<<rq.port_id) = 0x%x\n",(1<<rq.port_id));
if(verbose) printf("port_mask_src = 0x%x\n",port_mask_src);
if(verbose) printf("-----------------------\n\n");
add_to_learning_queue(rq,verbose);
already_in_learning_queue = 1;
}
}
}
////////////////////////////////////////////////////
// 3rd step: find the destination MAC in MAC table
////////////////////////////////////////////////////
mac_table_entry_t *entry_dst = NULL;
uint32_t port_mask_dst;
int is_bpdu;
if(mac_table_lookup(rq.dst, vent.fid, &entry_dst,verbose)) // lookup the destination MAC address in the table
{ // found:
port_mask_dst = entry_dst->port_mask_dst;
if(entry_dst->drop_when_dest) // destination MAC address is blocked? - drop the packet
{
if(verbose) printf("rtu_match: dropped (blocked destination MAC)\n");
//added by ML
rsp->prio = 0;
rsp->port_mask = 0;
/////////////
rsp->drop = 1;
return 0;
}
// if(entry_src->has_prio_dst) // check if the destination MAC has predefined priority and eventually add it to the selection table
//////////////
//ML: bug detected??
//////////////////
if(entry_dst->has_prio_dst) // check if the destination MAC has predefined priority and eventually add it to the selection table
{
prio_lookup[PRIO_DESTINATION] = entry_dst->prio_dst;
prio_override[PRIO_DESTINATION] = entry_dst->prio_override_dst;
}
is_bpdu = entry_dst->is_bpdu;
}
else { // destination MAC not found: broadcast the packet, put the entry into learning queue
if(CFG.port_cfg[rq.port_id].learning_enabled && (already_in_learning_queue==0))
{
add_to_learning_queue(rq,verbose);
already_in_learning_queue = 1;
}
if(CFG.port_cfg[rq.port_id].b_unrec == 0) // unrecongized request behaviour: drop packages
{
if(verbose) printf("rtu_match: dropped (urecognized packages dropped)\n");
rsp->prio = 0;
rsp->port_mask = 0;
/////////////
rsp->drop = 1;
return 0;
}
else
port_mask_dst = 0xffffffff;
is_bpdu = 0; // BPDU addresses are always registered in MAC table
}
////////////////////////////////////////////
// 4th step: make the final routing decision:
////////////////////////////////////////////
if(CFG.port_cfg[rq.port_id].forward_bpdu_only == 1 && !is_bpdu) // STP port blocked or learning
{
if(verbose) printf("rtu_match: dropped (non-BPDU packet on STP BLOCKED/LEARNING port)\n");
//added by ML
rsp->prio = 0;
rsp->port_mask = 0;
/////////////
rsp->drop = 1;
return 0;
}
rsp->port_mask = vent.port_mask & port_mask_dst; // generate the final port mask by anding the MAC-assigned destination ports with ports
// registered in current VLAN
//ML: why we don't do here like in case of prio src/dst??
// I mean: set prio_override only if has_prio=true
if(rq.has_prio)
prio_lookup[PRIO_PORT] = rq.prio;
// evaluate the final priority of the packet
rsp->prio = 0;
rsp->drop = 0;
int found = 0;
int i;
for(i=0; i<4; i++) // check for overriding priorities
if(prio_override[i])
{
rsp->prio = prio_lookup[i];
found = 1;
break;
}
if(!found)
{
for(i=0;i<4;i++)
if(prio_lookup[i] >= 0)
{
rsp->prio = prio_lookup[i];
break;
}
}
if(verbose) printf("rsp->port_mask[0x%x] = vent.port_mask[0x%x] & port_mask_dst[0x%x]\n", rsp->port_mask,vent.port_mask , port_mask_dst);
if(verbose) printf("port_mask_src = 0x%x\n", port_mask_src);
#ifdef DEBUG_SIMULATION
printf("prio_override[PRIO_SOURCE ] = 0x%x prio_lookup[PRIO_SOURCE ] = 0x%x\n",prio_override[0], prio_lookup[0]);
printf("prio_override[PRIO_DESTINATION] = 0x%x prio_lookup[PRIO_DESTINATION] = 0x%x\n",prio_override[1], prio_lookup[1]);
printf("prio_override[PRIO_VID ] = 0x%x prio_lookup[PRIO_VID ] = 0x%x\n",prio_override[2], prio_lookup[2]);
printf("prio_override[PRIO_PORT ] = 0x%x prio_lookup[PRIO_PORT ] = 0x%x\n",prio_override[3], prio_lookup[3]);
#endif
if(verbose) printf("rtu_match: accepted (portmask 0x%08x, priority: %d)\n", rsp->port_mask, rsp->prio);
return 0;
}
void set_mac(mac_addr_t mac, uint8_t a, uint8_t b, uint8_t c, uint8_t d, uint8_t e, uint8_t f)
{
mac[0]=a;
mac[1]=b;
mac[2]=c;
mac[3]=d;
mac[4]=e;
mac[5]=f;
}
documents/specifications/HDL/WRSW_RTU/wrsw_rtu_spec.txt 0 → 100644
View file @ 46a712c9
/*
-------------------------------------------------------------------------------
-- Title : RTU spec
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wrsw_rtu_spec.txt
-- Authors : Maciej Lipinski (maciej.lipinski@cern.ch)
-- Company : CERN BE-CO-HT
-- Created : 2010-10-06
-- Last update: 2010-10-08
-- Description: This file contain RTU specification for developers
-- of components which need to communicate with RTU
-- (mainly software developers).
-------------------------------------------------------------------------------
*/
1. What does RTU do ?:
RTU takes packet source & destination MAC addresses, VLAN ID
and priority and decides where and with what final priority (after
evaluating the per MAC-assigned priorities, per-VLAN priorities,
per-port and per-packet) the packet shall be routed.
2. Hardware interface (inputs/outputs to/from other HDL components)
2.1 ZBT SRAM
The main hash table is stored in ZBT SRAM. The memory is organized
in the following way:
addr 0: bucket 0 consists of [entry 1] [entry 2] [entry 3] [entry 4]
addr 1: bucket 1 consists of [entry 1] [entry 2] [entry 3] [entry 4]
"entry" in the memory is called "MAC entry" in this doc.
Its layout is defined in data_layout_in_mems.odt.
There are four entries in one bucket. The address of a bucket is calculated
as a hash of MAC and FID. The hash is defined by a polynomial (see 3.1).
A MAC entity is 8 words (8x32 bits), 5 words of data and 3 empty words
(to make the addressing easier).
An address of MAC entry has the following structure:
16 bit - bank
15 - 5 bits - hash address
4 - 3 bits - (bucket) number of MAC entry in the bucket (0-4)
2 - 0 bits - zeros (this is the address inside MAC entry)
2.2 N-port input/output interface.
SEE: wrsw_rtu.vhd
2.2 WISHBONE
The communication with uProcessor is performed through Wishbone Interface.
The interface is defined in wrsw_rtu_wb.wb, described in wrsw_rtu_wb.html
and implemented in wrsw_rtu_wb.vhd & wrsw_rtu_wb.h files.
It is described in details (software-wise) in section 3.
3. Software interface (talking with uProcessor):
RTU communicates with uP using Wishbone interface (generated from
wrsw_rtu_wb.wb, described in details in wrsw_rtu_wb.html).
The wishbone bus enables communication between uP and RTU by a set
of registers, memories and FIFOs. For software developers, the header
can be also generated using wrsw_rtu_wb.wb
(see documentation/specifications/hdlspec/WRSW_RTU/wrsw_rtu_wb.h).
3.1 RTU Global Control registers
Settings concerning entire RTU can be specified using this reg. It includes
- turning on/off the RTU (G_ENA),
- setting active memory banks (HT_BSEL & HCAM_BSEL)
- specifying polynomial for hash calculation
The bank which is set to be active is accessed (read) by the RTU (HW).
The bank which is NOT set to be active (inactive bank) is accessed by
the software through wishbone. HT_BSEL defines active bank of Main
hastbable which is accessed from SW by writing to MFIFO_R0 & MFIFO_R1
registers (see 3.4). HCAM_BSEL defines active bank of Hash collision
memory (HCAM) which is accessed from S/W directly at address 0x4000
(see wrsw_rtu_wb.html).
3.2 Port Control Register xxx
For each port xxx such a control register is defined. See wrsw_rtu_wb.html
for details of the register's layout.
3.3 Unrecognized request FIFO (UFIFO)
It is a set of FIFOs (r0 - r4) which hold data of unrecognized
(not found in hash table) MAC entry (source & destination MAC,
priority, PID, VID, etc). It shall be used by S/W for learning process.
There is an interrupt associated with the UFIFO which informs uP that
the there is data to be read from UFIFO.
3.4 Main hash table
The main hash table is kept in ZBT SRAM. It is addressed by hash calculated
using polynomial defined in "RTU Global Control Register" (see 3.1).
uP has only write access to this memory. It should be written by the
learning algorithm.
The main hash table is only read by RTU and only written to by S/W
(through MFIFO).
Basic write access to hash table shall be done in the following way:
- write 1 to MFIFO_R0 (AD_SEL defines whether AD_VAL is address or data),
- write address (to which data should be written) to MFIFO_R1,
- write 0 to MFIFO_R0 (AD_SEL defines whether AD_VAL is address or data),
- write data to MFIFO_R1 (minimum one MAC entry, so 5 words,
a bunch of data is considered for write to SRAM
only if the number of data words is greater or equal to
c_wrsw_entry_words_number (5), which is a parameter in:
/home/maciejl/wrdev_v3/hdl/common/global_defs.vhd).
The consecutive writes to MFIFO_R1 (AD_SEL = 0) are written to consecutive
SRAM memory addresses (atomic write) as long as one of the following
conditions is met:
- MFIFO is empty (all data written to MFIFO_R1 have been written to SRAM),
- next address is written to MFIFO_R1 (AD_SEL = 1); in such case,
an atomic write to SRAM is finished. and the next address is written
with the provided data in the successive atomic write.
The layout of the MAC entry is defined in data_layout_in_mems.odt.
The MAC entry fields are described in rtu_sim.c file.
If two consecutive MAC entries are to be written to SRAM,
they can be written with one atomic write operation
(e.g.: when writing new MAC entry to the same bucket, so the end_of_bucket
field needs to be updated in the previous MAC entry):
MAC entry address \
MAC entry data / atomic write
3 empty words /
MAC entry data /
Otherwise, write one MAC entry at a time, so :
MAC entry address \
MAC entry data / atomic write
MAC entry address \
MAC entry data / atomic write
[...]
The address supplied shall have the following layout
(defined also in data_layout_in_mems.odt) :
15 - 5 bits - hash address
4 - 3 bits - (bucket) number of MAC entry in the bucket (0-4)
2 - 0 bits - zeros (this is the address inside entry)
The data written by S/W is written to the inactive bank. It is not
used by RTU until the active bank is switched (see 3.1).
----------------------------------------------------------------------------
IMPORTANT: An exact mirror of SRAM memory needs to be kept in local memory.
This is because it is not possible to read ZBT SRAM from uP.
There is only write access from uP to ZBT SRAM through MFIFO.
----------------------------------------------------------------------------
S/W should know, by checking against local copy of Main hash table,
to which entry in given bucket, a MAC entry
should be written, and if there is free place in a give bucket.
3.5 Hash collisions memory (HCAM)
It is accessed directly (address = 0x4000), write and read.
MAC entry data layout provided in data_layout_in_mems.odt applies.
The address supplied shall have the following layout
(also in data_layout_in_mems.ods) :
8 bit - bank - is ignored, it is defined by HCAM_BSEL (see 3.1)
7 - 3 bits - HCAM address
2 - 0 bits - MAC entry word address
The data written to HCAM is written by RTU to the inactive bank. It is not
used by RTU until the active bank is switched (see 3.1).
Read access is also to inactive bank; therefore,
it is advised to keep mirror of HCAM in the local memory.
3.6 Aging bitmap for main hash table.
Aging memory is common for both banks ( and it is not cleared when
the banks are switched, it is clear-on-read). '1' indicates that the
"MAC entry" at the corresponding hash address in main hash table has
been accessed (matched).
Software should read the Aging bitmap periodically to check which MAC
entries are accessed, which shall enable implementation of aging
(deletion of MAC entries representing devices removed from the
network).
3.6 Aging register for HCAM
Each bit corresponds to one MAC entry in HCAM memory.
The same rules as in 3.6 apply.
3.7 VLAN table
Each word of VLAN table (32 bits) represents one VLAN entry
(no bank switching implemented). The layout of VLAN entry is defined
in data_layout_in_mems.ods
3.8 IRQ
There is only one interrupt generated by RTU. This is an interrupt
associated with the UFIFO.
There are four registers associated with interrupts in WB interface:
- rtu_eic_idr : interrupt disable
- rtu_eic_ier : interrupt enable
- rtu_eic_imr : interrupt mask
- rtu_eic_isr : interrupt status register
It is described in details in wrsw_rtu_wb.html file.
In general, all the interrupts inputted to WB interface
(by H/W) are multiplexed into one interrupt signal (see: wb_irq_o).
When the uP receives it, it needs to read 'rtu_eic_isr' register
to check which irq it was.
The interrupt associated with UFIFO does not required to be cleaned
(i.e. by writing rtu_eic_isr). This is because the interrupt is
triggered by the level of UFIFO empty signal. Once UFIFO is read out,
the interrupt is cleaned automatically.
For example S/W implementation of the interrupts (generated by WB)
handling, please see the code:
trunk/software/drivers/wr_vic/wr_vic.c
4 HASH address
Below table gives the kinds of hashes which are implemented by RTU
and their hex representation of polynomial (to be supplied to RTU
Global Control registers, see 3.1).
-----------------------------------------------------------
--| name | polly equation | polly (hex) |
-----------------------------------------------------------
--| CRC-16-CCITT | 1+x^5+x^12+x^16 | 0x1021 |
--| CRC-16-IBM | 1+x^2+x^15+x^16 | 0x8005 |
--| CRC-16-DECT | 1+x^3+x^7+x^8+x^10+x^16 | 0x0589 |
-----------------------------------------------------------
Please, refer an example S/W implementation of these hashes in the file:
/home/maciejl/wrdev_v3/software/tests/test_rtu/rtu_common.c
If you want to implement the calculation in a more efficient way,
please make sure you've got the same result as the example implementations
(which were tested against RTU H/W implementation).
5 RTU algorithm
The exact lookup algorithm is described in rtu_sim.c file. This algorithm
was used to simulate and test RTU.
--------------------------------------------------------------------------
AUXILIARY:
--------------------------------------------------------------------------
0) Wishbone interface generator:
The project is detailed here: http://www.ohwr.org/projects/wishbone-gen.
In short, the *.wb file enables to generate:
- vhdl/verilog source,
- C header
- html description of the interface
For RTU, the .wb file, html info and C header can be found here:
documentation/specifications/hdlspec/WRSW_RTU/ .
The vhd file is in RTU sources: hdl/modules/wrsw_rtu/wrsw_rtu_wb.vhd.
1) RTU spec files (documentation/specifications/hdlspec/WRSW_RTU)
wrsw_rtu_spec.txt -------- this file.
data_layout_in_mems.ods -- here is defined the layout of RTU memories:
MAC entry, VLAN entry
rtu_sim.c ---------------- software simulation of the hardware algorithm,
based on this file hardware algorithm
was implemented (much easier to read for S/W
people than HDL code :). It is used in RTU test
application. There outcome of this simulation
is compared with the outcome of HW implementation
when the test application is run.
wrsw_rtu_wb.wb ----------- Wishbone file, defines RTU's wishbone interface,
based on it, the below files are generated
(and wrsw_rtu_wb.vhd found in RTU sources) :
wrsw_rtu_wb.h ------------ header with S/W addresses
wrsw_rtu_wb.html --------- describes the RTU's Wishbone interface in
user-friendly way (LOOK HERE)
2) RTU test application (/software/tests/test_rtu/):
-------------------------- application written in C, it compares outcome
of the hardware matching and software simulation.
rtu_test_main.c ---------- detailed description of how the test app. works
can be found here
rtu_hw.c ----------------- the interface with hardware is implemented here
rtu_sim.c ---------------- software simulation of the hardware algorithm,
based on this file hardware algorithm was
implemented (much easier to read for S/W people
than HDL code :). The outcome of this simulation
is compared with the outcome of HW implementation
when the test application is run
3) Example code:
- IRQ handling ------------ here: trunk/software/drivers/wr_vic/wr_vic.c
\ No newline at end of file
documents/specifications/HDL/WRSW_RTU/wrsw_rtu_wb.h 0 → 100644
View file @ 46a712c9
/*
Register definitions for slave core: Routing Table Unit (RTU)
* File : wrsw_rtu_wb.h
* Author : auto-generated by wbgen2 from wrsw_rtu_wb.wb
* Created : Wed Oct 6 11:42:20 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_rtu_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRSW_RTU_WB_WB
#define __WBGEN2_REGDEFS_WRSW_RTU_WB_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: RTU Global Control Register */
/* definitions for field: Main table bank select in reg: RTU Global Control Register */
#define RTU_GCR_HT_BSEL WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Hash collision table (HCAM) bank select in reg: RTU Global Control Register */
#define RTU_GCR_HCAM_BSEL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: RTU Global Enable in reg: RTU Global Control Register */
#define RTU_GCR_G_ENA WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Hash Poly in reg: RTU Global Control Register */
#define RTU_GCR_POLY_VAL_MASK WBGEN2_GEN_MASK(8, 16)
#define RTU_GCR_POLY_VAL_SHIFT 8
#define RTU_GCR_POLY_VAL_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define RTU_GCR_POLY_VAL_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: Aging register for HCAM */
/* definitions for register: Port Control Register 0 */
/* definitions for field: Learning enable in reg: Port Control Register 0 */
#define RTU_PCR0_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 0 */
#define RTU_PCR0_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 0 */
#define RTU_PCR0_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 0 */
#define RTU_PCR0_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 0 */
#define RTU_PCR0_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR0_PRIO_VAL_SHIFT 4
#define RTU_PCR0_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR0_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 0 */
#define RTU_PCR0_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 1 */
/* definitions for field: Learning enable in reg: Port Control Register 1 */
#define RTU_PCR1_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 1 */
#define RTU_PCR1_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 1 */
#define RTU_PCR1_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 1 */
#define RTU_PCR1_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 1 */
#define RTU_PCR1_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR1_PRIO_VAL_SHIFT 4
#define RTU_PCR1_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR1_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 1 */
#define RTU_PCR1_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 2 */
/* definitions for field: Learning enable in reg: Port Control Register 2 */
#define RTU_PCR2_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 2 */
#define RTU_PCR2_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 2 */
#define RTU_PCR2_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 2 */
#define RTU_PCR2_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 2 */
#define RTU_PCR2_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR2_PRIO_VAL_SHIFT 4
#define RTU_PCR2_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR2_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 2 */
#define RTU_PCR2_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 3 */
/* definitions for field: Learning enable in reg: Port Control Register 3 */
#define RTU_PCR3_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 3 */
#define RTU_PCR3_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 3 */
#define RTU_PCR3_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 3 */
#define RTU_PCR3_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 3 */
#define RTU_PCR3_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR3_PRIO_VAL_SHIFT 4
#define RTU_PCR3_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR3_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 3 */
#define RTU_PCR3_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 4 */
/* definitions for field: Learning enable in reg: Port Control Register 4 */
#define RTU_PCR4_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 4 */
#define RTU_PCR4_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 4 */
#define RTU_PCR4_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 4 */
#define RTU_PCR4_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 4 */
#define RTU_PCR4_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR4_PRIO_VAL_SHIFT 4
#define RTU_PCR4_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR4_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 4 */
#define RTU_PCR4_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 5 */
/* definitions for field: Learning enable in reg: Port Control Register 5 */
#define RTU_PCR5_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 5 */
#define RTU_PCR5_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 5 */
#define RTU_PCR5_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 5 */
#define RTU_PCR5_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 5 */
#define RTU_PCR5_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR5_PRIO_VAL_SHIFT 4
#define RTU_PCR5_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR5_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 5 */
#define RTU_PCR5_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 6 */
/* definitions for field: Learning enable in reg: Port Control Register 6 */
#define RTU_PCR6_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 6 */
#define RTU_PCR6_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 6 */
#define RTU_PCR6_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 6 */
#define RTU_PCR6_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 6 */
#define RTU_PCR6_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR6_PRIO_VAL_SHIFT 4
#define RTU_PCR6_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR6_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 6 */
#define RTU_PCR6_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 7 */
/* definitions for field: Learning enable in reg: Port Control Register 7 */
#define RTU_PCR7_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 7 */
#define RTU_PCR7_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 7 */
#define RTU_PCR7_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 7 */
#define RTU_PCR7_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 7 */
#define RTU_PCR7_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR7_PRIO_VAL_SHIFT 4
#define RTU_PCR7_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR7_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 7 */
#define RTU_PCR7_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 8 */
/* definitions for field: Learning enable in reg: Port Control Register 8 */
#define RTU_PCR8_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 8 */
#define RTU_PCR8_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 8 */
#define RTU_PCR8_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 8 */
#define RTU_PCR8_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 8 */
#define RTU_PCR8_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR8_PRIO_VAL_SHIFT 4
#define RTU_PCR8_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR8_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 8 */
#define RTU_PCR8_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 9 */
/* definitions for field: Learning enable in reg: Port Control Register 9 */
#define RTU_PCR9_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 9 */
#define RTU_PCR9_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 9 */
#define RTU_PCR9_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 9 */
#define RTU_PCR9_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 9 */
#define RTU_PCR9_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR9_PRIO_VAL_SHIFT 4
#define RTU_PCR9_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR9_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 9 */
#define RTU_PCR9_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Interrupt disable register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt disable register */
#define RTU_EIC_IDR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt enable register */
#define RTU_EIC_IER_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt mask register */
#define RTU_EIC_IMR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt status register */
#define RTU_EIC_ISR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
/* definitions for field: Destination MAC address least-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
#define RTU_UFIFO_R0_DMAC_LO_MASK WBGEN2_GEN_MASK(0, 32)
#define RTU_UFIFO_R0_DMAC_LO_SHIFT 0
#define RTU_UFIFO_R0_DMAC_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_UFIFO_R0_DMAC_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
/* definitions for field: Destination MAC address most-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
#define RTU_UFIFO_R1_DMAC_HI_MASK WBGEN2_GEN_MASK(0, 16)
#define RTU_UFIFO_R1_DMAC_HI_SHIFT 0
#define RTU_UFIFO_R1_DMAC_HI_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define RTU_UFIFO_R1_DMAC_HI_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
/* definitions for field: Source MAC address least-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
#define RTU_UFIFO_R2_SMAC_LO_MASK WBGEN2_GEN_MASK(0, 32)
#define RTU_UFIFO_R2_SMAC_LO_SHIFT 0
#define RTU_UFIFO_R2_SMAC_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_UFIFO_R2_SMAC_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
/* definitions for field: Source MAC address most-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
#define RTU_UFIFO_R3_SMAC_HI_MASK WBGEN2_GEN_MASK(0, 16)
#define RTU_UFIFO_R3_SMAC_HI_SHIFT 0
#define RTU_UFIFO_R3_SMAC_HI_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define RTU_UFIFO_R3_SMAC_HI_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
/* definitions for field: VLAN Identifier in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_VID_MASK WBGEN2_GEN_MASK(0, 12)
#define RTU_UFIFO_R4_VID_SHIFT 0
#define RTU_UFIFO_R4_VID_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define RTU_UFIFO_R4_VID_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Priority in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_PRIO_MASK WBGEN2_GEN_MASK(12, 3)
#define RTU_UFIFO_R4_PRIO_SHIFT 12
#define RTU_UFIFO_R4_PRIO_W(value) WBGEN2_GEN_WRITE(value, 12, 3)
#define RTU_UFIFO_R4_PRIO_R(reg) WBGEN2_GEN_READ(reg, 12, 3)
/* definitions for field: Port ID in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_PID_MASK WBGEN2_GEN_MASK(16, 4)
#define RTU_UFIFO_R4_PID_SHIFT 16
#define RTU_UFIFO_R4_PID_W(value) WBGEN2_GEN_WRITE(value, 16, 4)
#define RTU_UFIFO_R4_PID_R(reg) WBGEN2_GEN_READ(reg, 16, 4)
/* definitions for field: VID valid in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_HAS_VID WBGEN2_GEN_MASK(20, 1)
/* definitions for field: PRIO valid in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_HAS_PRIO WBGEN2_GEN_MASK(21, 1)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
#define RTU_UFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
#define RTU_UFIFO_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 7)
#define RTU_UFIFO_CSR_USEDW_SHIFT 0
#define RTU_UFIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define RTU_UFIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
/* definitions for field: Address/data select in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
#define RTU_MFIFO_R0_AD_SEL WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
/* definitions for field: Address/data value in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
#define RTU_MFIFO_R1_AD_VAL_MASK WBGEN2_GEN_MASK(0, 32)
#define RTU_MFIFO_R1_AD_VAL_SHIFT 0
#define RTU_MFIFO_R1_AD_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_MFIFO_R1_AD_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 6)
#define RTU_MFIFO_CSR_USEDW_SHIFT 0
#define RTU_MFIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define RTU_MFIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for RAM: Hash collisions memory (HCAM) */
#define RTU_HCAM_BYTES 0x00000800 /* size in bytes */
#define RTU_HCAM_WORDS 0x00000200 /* size in 32-bit words, 32-bit aligned */
/* definitions for RAM: Aging bitmap for main hashtable */
#define RTU_ARAM_MAIN_BYTES 0x00000400 /* size in bytes */
#define RTU_ARAM_MAIN_WORDS 0x00000100 /* size in 32-bit words, 32-bit aligned */
/* definitions for RAM: VLAN table (VLAN_TAB) */
#define RTU_VLAN_TAB_BYTES 0x00004000 /* size in bytes */
#define RTU_VLAN_TAB_WORDS 0x00001000 /* size in 32-bit words, 32-bit aligned */
/* [0x0]: REG RTU Global Control Register */
#define RTU_REG_GCR 0x00000000
/* [0x4]: REG Aging register for HCAM */
#define RTU_REG_AGR_HCAM 0x00000004
/* [0x8]: REG Port Control Register 0 */
#define RTU_REG_PCR0 0x00000008
/* [0xc]: REG Port Control Register 1 */
#define RTU_REG_PCR1 0x0000000c
/* [0x10]: REG Port Control Register 2 */
#define RTU_REG_PCR2 0x00000010
/* [0x14]: REG Port Control Register 3 */
#define RTU_REG_PCR3 0x00000014
/* [0x18]: REG Port Control Register 4 */
#define RTU_REG_PCR4 0x00000018
/* [0x1c]: REG Port Control Register 5 */
#define RTU_REG_PCR5 0x0000001c
/* [0x20]: REG Port Control Register 6 */
#define RTU_REG_PCR6 0x00000020
/* [0x24]: REG Port Control Register 7 */
#define RTU_REG_PCR7 0x00000024
/* [0x28]: REG Port Control Register 8 */
#define RTU_REG_PCR8 0x00000028
/* [0x2c]: REG Port Control Register 9 */
#define RTU_REG_PCR9 0x0000002c
/* [0x40]: REG Interrupt disable register */
#define RTU_REG_EIC_IDR 0x00000040
/* [0x44]: REG Interrupt enable register */
#define RTU_REG_EIC_IER 0x00000044
/* [0x48]: REG Interrupt mask register */
#define RTU_REG_EIC_IMR 0x00000048
/* [0x4c]: REG Interrupt status register */
#define RTU_REG_EIC_ISR 0x0000004c
/* [0x50]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
#define RTU_REG_UFIFO_R0 0x00000050
/* [0x54]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
#define RTU_REG_UFIFO_R1 0x00000054
/* [0x58]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
#define RTU_REG_UFIFO_R2 0x00000058
/* [0x5c]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
#define RTU_REG_UFIFO_R3 0x0000005c
/* [0x60]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_REG_UFIFO_R4 0x00000060
/* [0x64]: REG FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
#define RTU_REG_UFIFO_CSR 0x00000064
/* [0x68]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
#define RTU_REG_MFIFO_R0 0x00000068
/* [0x6c]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
#define RTU_REG_MFIFO_R1 0x0000006c
/* [0x70]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_REG_MFIFO_CSR 0x00000070
#endif
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-- -*- Mode: LUA; tab-width: 2 -*-
PCR_template = reg {
name = "Port Control Register";
description = "Register controlling the mode of certain RTU port.";
prefix = "PCR";
field {
name = "Learning enable";
description = "1: enables learning process on this port. Unrecognized requests will be put into UFIFO\
0: disables learning. Unrecognized requests will be either broadcast or dropped.";
prefix = "LEARN_EN";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Pass all packets";
description = "1: all packets are passed (depending on the rules in RT table). \
0: all packets are dropped on this port.";
prefix = "PASS_ALL";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Pass BPDUs";
description = "1: BPDU packets (with dst MAC 01:80:c2:00:00:00) are passed according to RT rules. This setting overrides PASS_ALL.\
0: BPDU packets are passed according to RTU rules only if PASS_ALL is set.[ML by modified]";
prefix = "PASS_BPDU";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Fix priority";
description = "1: Port has fixed priority of value PRIO_VAL. It overrides the priority coming from the endpoint\
0: Use priority from the endpoint";
prefix = "FIX_PRIO";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Priority value";
description = "Fixed priority value for the port. Used instead the endpoint-assigned priority when FIX_PRIO = 1";
prefix = "PRIO_VAL";
type = SLV;
align = 4;
size =3 ;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Unrecognized request behaviour";
description = "Sets the port behaviour for all unrecognized requests:\
0: packet is dropped\
1: packet is broadcast";
prefix = "B_UNREC";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
-- Mirroring Control fields go here.
};
peripheral {
name = "Routing Table Unit (RTU)";
prefix="rtu";
hdl_entity="wrsw_rtu_wb";
-- Port Configuration Register
reg {
name = "RTU Global Control Register";
description = "Control register containing global (port-independent) settings of the RTU.";
prefix = "GCR";
field {
name = "Main table bank select";
description = "Selects active bank of RTU hashtable (ZBT).\
0: bank 0 is used by lookup engine and bank 1 can be accessed using MFIFO\
1: bank 1 is used by lookup engine and bank 0 can be accessed using MFIFO";
type = BIT;
prefix = "HT_BSEL";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Hash collision table (HCAM) bank select";
description = "Selects active bank of RTU extra memory for colliding hashes.\
0: bank 0 is used by lookup engine\
1: bank 1 is used by lookup engine";
type = BIT;
prefix = "HCAM_BSEL";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "RTU Global Enable";
description = "Global RTU enable bit. Overrides all port settings.\
0: RTU is disabled. All packets are dropped.\
1: RTU is enabled.";
type = BIT;
prefix = "G_ENA";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Hash Poly";
description = "Determines the polynomial used for hash computation. Currently available: 0x1021, 0x8005, 0x0589 ";
type = SLV;
prefix = "POLY_VAL";
align = 8;
size = 16 ;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
clock = "zbt_clk_i";
};
-- TXTSU interrupts
irq {
name = "UFIFO Not Empty IRQ";
description = "Interrupt active when there are some requests in UFIFO.";
prefix = "nempty";
trigger = LEVEL_0;
};
fifo_reg {
name = "Unrecognized request FIFO (UFIFO)";
description = "FIFO containing all RTU requests for which matching entries haven't been found. CPU reads these requests,\
evaluates them and updates the RTU tables accordingly.";
prefix = "UFIFO";
direction = CORE_TO_BUS;
size = 128;
flags_dev = {FIFO_FULL, FIFO_EMPTY};
flags_bus = {FIFO_EMPTY, FIFO_COUNT};
--clock = "zbt_clk_i";
-- clock = ""; - make it asynchronous if you want
field {
name = "Destination MAC address least-significant part";
description = "Bits [31:0] of packet destination MAC address";
prefix = "DMAC_LO";
type = SLV;
size = 32;
};
field {
name = "Destination MAC address most-significant part";
description = "Bits [47:32] of packet destination MAC address";
prefix = "DMAC_HI";
type = SLV;
size = 16;
};
field {
name = "Source MAC address least-significant part";
description = "Bits [31:0] of packet source MAC address";
prefix = "SMAC_LO";
type = SLV;
size = 32;
};
field {
name = "Source MAC address most-significant part";
description = "Bits [47:32] of packet source MAC address";
prefix = "SMAC_HI";
type = SLV;
size = 16;
};
field {
name = "VLAN Identifier";
description = "VLAN ID of the packet (from the endpoint)";
prefix = "VID";
size = 12;
type = SLV;
align = 32;
};
field {
name = "Priority";
description = "Priority value (from the endpoint)";
prefix = "PRIO";
size = 3;
align = 4;
type = SLV;
};
field {
name = "Port ID";
description = "Identifier of RTU port to which came the request.";
prefix = "PID";
size = 4;
align = 4;
type = SLV;
};
field {
name = "VID valid";
description = "1: VID value is valid\
0: packet had no VLAN ID";
prefix = "HAS_VID";
align = 4;
type = BIT;
};
field {
name = "PRIO valid";
description = "1: PRIO value is valid\
0: packet had no priority assigned";
prefix = "HAS_PRIO";
type = BIT;
};
};
ram {
name = "Hash collisions memory (HCAM)";
description = "Memory block containing the 'tails' for hashes which have more than 4 entries and don't fit into a single bucket of main ZBT hashtable. \
<b>Note:</b> MSB of the address is the bank select bit. ";
prefix = "HCAM";
width = 32;
size = 32 * 8 * 2; -- 32 entries * 8 words per entry * 2 banks
access_dev = READ_ONLY;
access_bus = READ_WRITE;
clock = "zbt_clk_i"; --async?
};
ram {
name = "Aging bitmap for main hashtable";
description = "Each bit in this memory reflects the state of corresponding entry in main hashtable:\
0: entry wasn't matched\
1: entry was matched at least once.\
CPU reads this bitmap and subsequently clears it every few seconds to update the aging counters.";
prefix = "ARAM_MAIN";
width = 32;
size = 8192 / 32; -- 8192 bits
access_dev = READ_WRITE;
access_bus = READ_WRITE;
--[changed 6/10/2010] clock = "zbt_clk_i";
--clock = "zbt_clk_i"; --async?
};
ram {
name = "VLAN table (VLAN_TAB)";
description = "It stores VLAN-related information identified by VLAN ID (VID)";
prefix = "VLAN_TAB";
width = 32;
size = 4096 ; -- 4096 entries as defined in 802.1Q-2005, page 12
access_dev = READ_ONLY;
access_bus = READ_WRITE;
-- --[changed 6/10/2010] clock = "zbt_clk_i";
--clock = "zbt_clk_i"; --async?
};
reg {
name = "Aging register for HCAM";
description = "Each bit in this register reflects the state of corresponding entry in HCAM:\
0: entry wasn't matched\
1: entry was matched at least once.\
CPU reads this bitmap and subsequently clears it every few seconds to update the aging counters.";
prefix = "AGR_HCAM";
field {
name = "Aging register value";
type = SLV;
size = 32;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
clock = "zbt_clk_i";
-- clock = "zbt_clk_i"; --async?
};
fifo_reg {
name = "Main hashtable CPU access FIFO (MFIFO)";
description = "FIFO for writing to main hashtable";
prefix = "MFIFO";
direction = BUS_TO_CORE;
size = 64;
flags_dev = {FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_EMPTY, FIFO_FULL, FIFO_COUNT};
field {
name = "Address/data select";
description = "1: AD_VAL contains new memory address\
0: AD_VAL contains data word to be written at current memory address. Then, the address is incremented";
prefix = "AD_SEL";
type = BIT;
};
field {
name = "Address/data value";
description = "Value of new memory address (when AD_SEL = 1) or data word to be written (when AD_SEL = 0)";
prefix = "AD_VAL";
type = SLV;
align =32;
size = 32;
};
clock = "zbt_clk_i";
};
};
function gen_PCRs(num_pcrs)
local i;
for i=0,num_pcrs-1 do
local rp = deepcopy(PCR_template);
rp.name = rp.name.." "..i;
rp.prefix = rp.prefix..i;
table.insert(periph, rp);
end
end
gen_PCRs(10);
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/*
-------------------------------------------------------------------------------
-- Title : SWcore pseudocode
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wrsw_hdl_spec.txt
-- Authors : Maciej Lipinski (maciej.lipinski@cern.ch)
-- Company : CERN BE-CO-HT
-- Created : 2012-01-11
-- Last update: 2012-01-211
-- Description: this is kind-of-pseudo code which attempts to explain how the
-- SWcore and its output queues are working.
-- It does not meant to compile.
-------------------------------------------------------------------------------
*/
#define OUT_QUEUE_NUMBER 8;
#define PORT_NUMBER 8; //whatever
#define FBM_MEMORY_SIZE 123456; //whatever
typedef struct {
FIFO single_prio_fifo; // this is an abstract type of First In First Out
boolean empty; // true if the FIFO is empty
} swcore_out_quque_t;
typedef struct {
ETHERNET_FRAME buf; // here the frame is stored
} swcore_FBM_entry_t;
typedef struct {
boolean valid; // true if the rest of the data is valid
int address; // address of the first page of the frame in the memory
int port_mask;// to which ports the frame is to be forwarded (e.g.: 0101 => forward to
// ports: 0 and 2,
int priority; // with what priority
} swcore_transfer_t;
// here we declare output queues for all the ports and their priorities
swcore_out_quque_t output[PORT_NUMBER][OUT_QUEUE_NUMBER];
// the Fabulously Big Memory (FBM)
swcore_FBM_entry_t fbm_memory[FBM_MEMORY_SIZE];
//this is used to transfer frame from input ports to output ports
swcore_transfer_t transfer[PORT_NUMBER];
boolean receive(ETHERNET_FRAME *buf, int port_number)
{
/*
* this function receives Ethernet frames from the physical interface of the port_number
*/
}
boolean send(ETHERNET_FRAME *buf, int port_number)
{
/*
* this function sends Ethernet frames to the physical interface of the port_number
*/
}
boolean rtu(ETHERNET_FRAME *buf, int *port_mask, int *priority)
{
/*
* here, the routing decision is taken
* the output of this function are:
* - the decision to which ports the frame should go (port_mask)
* - the decision what is the priority of the frame
* - (in the future) it will also tell whether it is broadcast or unicast
*/
}
int mmu()
{
/*
* Memory Management Unit - returns the address of the page allocated in the FBM memory
*/
}
/*
this function takes data from an ports' input and makes it available to ports' output
*/
void arbiter(int port_mask,int priority,int address, int port_number /*input*/)
{
transfer[port_number].address = address;
transfer[port_number].port_mask = port_mask;
transfer[port_number].priority = priority;
transfer[port_number].valid = TRUE;
// here we wait for all the appropriate ports' outputs to read the data
while (transfer[port_number].port_mask != 0);
transfer[port_number].valid = FALSE;
}
/*
input block, this is per port
*/
void input_block(int port_number)
{
ETHERNET_FRAME buf; //an abstract type to store a received Ethernet frame
int port_mask;
int priority;
int address;
while(1)
{
if( receive(&buf,port_number) == TRUE )
{
// ask Routing Table Unit
rtu(&buf, &port_mask, &priority);
//acquire address of the first page
address = mmu();
//store in memory
fbm_memory[address].buf = buf;
// forward a pointer to the frame to all the appropriate ports
// waits until all the appropriate ports read the data
arbiter(port_mask, priority, address);
}
}
}
void output_block(int port_number)
{
int address;
/* the below two whiles are done simultaneously (try to imagine :)*/
while(1)
{
for(int i=0; i<PORT_NUMBER; i++)
{
if( (transfer[i].port_mask >> port_number) & 0x1 ) // we check all the input ports for a frame
{ // destined to the port
int addresss = transfer[i].address;
int priority = transfer[i].priority;
// put the address of the first page of the frame into the output fifo for a given priority
output[port_number][priority].single_prio_fifo.push(address);
output[port_number][priority].empty = FALSE;
// indicate that the frame was received by the output port
transfer[i].port_mask = transfer[i].port_mask & (0x1 << port_number);
}
}
}
// here is the very "advanced" output scheduling algorithm
while(1)
{
for(int i=OUT_QUEUE_NUMBER-1; i>=0; i--)
{
if( output[port_number][i].empty == FALSE)
{
// get the pointer to the oldest frame in the output queue
address = output[port_number][i].single_prio_fifo.front();
// send the frame
send(fbm_memory[address], port_number);
}
}
}
}
void swcore_main()
{
int port_number;
/*
* if you imagine that all the below functions are executed simultaneusly,
* then you have the idea how the SWCORE works
*/
// PORT_NUMBER input ports
input_block(0);
input_block(1);
input_block(2);
input_block(3);
input_block(4);
input_block(5);
input_block(6);
input_block(7);
// PORT_NUMBER of output ports
input_block(0);
input_block(1);
input_block(2);
input_block(3);
input_block(4);
input_block(5);
input_block(6);
input_block(7);
}
\ No newline at end of file
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/*
-------------------------------------------------------------------------------
-- Title : SWcore HDL documentation
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wrsw_hdl_spec.txt
-- Authors : Maciej Lipinski (maciej.lipinski@cern.ch)
-- Company : CERN BE-CO-HT
-- Created : 2011-11-28
-- Last update: 2011-11-28
-- Description: This file contain description of SWcore and its components for anyone
-- who would like (fear !!!) to make any modifications to that module
-- or even worse...for someone how (for some strange reason) would
-- like to understand how it works.
-------------------------------------------------------------------------------
*/
The specification according to which the SWcore was created is in the following file
(swcore_spec.pdf). Please, read the specification first before reading this document.
In this document I assumes your prior knowledge of the spec(swcore_spec.pdf).
Refer to the swcore_architecture.pdf for a drawing of the architecture of the SWcore
(I promise to redraw it in some graphical tool when I find time, sorry for the current
poor quality).
SWcore interfaces with Endpoints and RTU@HW (another HDL modules). As of the time of writing,
the interface between Endpoints and SWcore is the Fabric Interface but it will have to be
eventually changed to pipelined Wishbone.
SWcore is generic in the following regards:
- number of ports (c_swc_num_ports)
- number of output priority queues (c_swc_output_prio_num) and
- output queues' size (c_swc_output_fifo_size)
- some more internal stuff like page number
All the parameters are defiend in the package file: swc_swcore_pkg.vhd
1. swc_core.vhd
This is the top entity which just contains and connects different componetns of the SWcore.
It can be configured to instanciate a give number of ports.
SWcore interfaces with Endpoint modules using two components:
- swc_input_block.vhd
- swc_output_block.vhd
SWcore interfaces with RTU using swc_input_block.vhd
2. INPUT_BLOCK (swc_input_block.vhd)
This block controls input to SW Core. It consists of a three Finite State Machines (FSMs):
1) Read FSM - reads information from Fabric Interface and stores it in FIFO:
* it speaks with the outside world (Endpoint) through Fabric IF (later pipelined WB)
* it waits for the decision (port_mask) from RTU
* stores data into FIO
2) Write FSM - reads data from FIFO and writes it into write pump
* it speaks with the multiport memory (swc_packet_mem.vhd)
* it writes to an allocated in advanced address
3) Page FSM - allocates pages in advance and sets usecnt of pages, i.e
* it allocates in advance one page to be used as the first page
of the pck (pckstart)
* it allocates in advnace one page to be used within the pck (interpck)
* it sets usecnt of pckstart page if it's different then the one set
durring allocation
* it sets usecnt of interpck page if it's different then the one set
durring allocation
Speaking with the outside world
This block reads the incoming package (Ethernet frame) through Fabric IF from the Endpoint and
reads forwarding decision from RTU. It stores the package in the FIFO.
The Endpoint forwards the Destination MAC, Source MAC, VLAN and priority to RTU module directly.
The SWcore only waits for the forwarding decision (port_mask, drop, prio).
Speaking with the SWcore guts:
1) Package Transfer Arbiter (swc_pck_transfer_arbiter.vhd) - input block forward to the Arbiter
the port_mask (once it is received from the RTU), the size of the package received and the
address of the first allocated page.
2) Mulitport Memory (swc_pcaket_mem.vhd) - the Write FSM writes the package from the FIFO
to the Multiport Memory at the allocated addresses (page by page)
3) MMEMORY_MANAGEMENT_UNIT (swc_multiport_page_allocator.vhd) - the input block (Page FSM) requests
from MMU a free memory page address (in advance: when waiting for new package or when
writing page). This page address is used when writing pacakge to multiport memory.
4) PCK_PAGES_FREEEING_MODULE (swc_multiport_pck_pg_free_module.vhd) - if a pacakge is dropped
during tranfser (so when we started writing to the Multiport Memory), we need to free
the already allocated and written to pages. This is what the PCK_PAGES_FREEING_MODULE is used
interfaced for.
3. OUTPUT_BLOCK (swc_output_block.vhd)
Speaking with the outside world:
It outputs a pacakge via Fabric IF to an Endpoint
Speaking with the SWcore guts:
1) TRANSER_ARBITER (swc_pck_transfer_arbiter.vhd) - output block receives from the Arbiter :
- the address of the first page of the packge,
- the priority of the package
- the size of the packge
2) MUPTIPORT_MEMORY (swc_packet_mem.vhd) - output block starts reading the package to be sent
from the Multiport Memory from the address transfed by the Transfer Arbiter.
3) PCK_PAGES_FREEEING_MODULE (swc_multiport_pck_pg_free_module.vhd) - once the package is
sent, the output block it frees the allocated pages using PCK_PAGE_FREEING_MODULE.
There is only one FSM which controls the OUTPUT_BLOCK, it simply
- waits until there is something in an output queue (not_empty_array vector is non-zero)
- request reading the page (read from the output queue) from the Multiport Memory
- reads the package from the Mulitport Memory
- frees the page address
Internal components of the OUTPUT_BLOCK:
3.1 RD_ENCODE (swc_prio_encoder.vhd)
It decides which output queue should be read, what it does is:
- it takes an input array (not_empty_array) of bits, each bits is equivalent to one priority. If
a bit is '1', it means that the output queue of the given priority is not empty, MSB is lowest
priority, LSB is the highest priority 0.
- the encoder detects the first least significant '1' (the most to the right) and returns two values:
a vector with a single '1' at the position of the first least significant '1' and the numerical
value of its position, e.g.:
in_i = 1110101011000
out_o = 3
onehot_o = 0000000001000
This is used in deciding which output queue to read first.
3.2 SSRAM (generic_ssram_dualport_singleclock)- the output queues are implemented as a single
SSRAM. The ram only stores pck_size and page_addres. The priority of the pacakge is encoded
into the address of the SSRAM under which the information is stored.
3.3 PRIO_QUEUE_CTRL (swc_ob_prio_queue.vhd)
Each piece of SSRAM allocated for a given priority is like a round buffer. So for each of this
memory space there is instanciated a PRIO_QUEUE_CTRL which controls the read/write address of this
memory space (it tracks the head/tail).
4. TRANSER_ARBITER (swc_pck_transfer_arbiter.vhd)
This module does the forwarding trick !!
It takes the following inputs from an INPUT_BLOCK:
- port mask
- page address
- priority
- package size
And forwards this information to OUTPUT_BLOCK specified by the port mask.
Speaking with the SWcore guts:
1) INPUT_BLOCK (swc_input_block.vhd) - the arbiter takes the info (port mask, page addr,
priority, size) about a correctly received package from the input block
2) OUTPUT_BLOCK (swc_output_block.vhd) - the arbiter forwards the info (port mask, page addr,
priority, size) about a correctly received packge to the appropriate output blocks.
How the stuff works:
- INPUT_BLOCK writes info (port mask, page addr, priority, size) about a correctly received package
to the TRANSER_ARBITER
- the TRANSFER_INPUT block instanciated for the port from which the info came, makes the
info avilable for the TRANSFER_OUTPUT blocks and waits for all the proper TRANSFER_OUTPUT blocks
to read the info (they clear appropriate bits in the mask (pto_read_mask)
- once all the appropriate (defined by port_mask) TRANSFER_OUTPUT blocks
(so all the appropriate OUTPUT_BLOCKs, so all the appropriate ports) have read the info,
the TRANSFER_INPUT send ack to the INPUT_BLOCK
Internal components of the TRANSER_ARBITER:
4.1 TRANSFER_INPUT (swc_pck_transfer_input.vhd)
Instanciated for each INPUT_BLOCK, it manages the transfer of the data. It takes the info
(port mask, page addr, priority, size) from the INPUT_BLOCK and make it available for
OUTPUT_BLOCKs (through TRANSFER_OUTPUT, below) as long as all the OUTPUT_BLOCKs read it.
It ackes successful reception of the info to all the OUTPUT_BLOCKs
4.2. TRANSFER_OUTPUT (swc_pck_transfer_output.vhd)
Instanciated for each OUTPUT_BLOCK, it manages the transfer of the data. It takes the info
(page addr, priority, size) from the TRANSFER_INPUT and make it available to
the OUTPUT_BLOCK. It acknowledges to the TRANSFER_INPUT block that it read the data.
5. MUPTIPORT_MEMORY (swc_packet_mem.vhd)
Here we enable 'c_swc_num_ports' ports to write and read to/from
shared memory. We assume we know the memory page (provided by page
allocator/deallocator, another component).
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
Packets from each port are written/read to/from memory pumps:
- WRPUMP (swc_packet_mem_write_pump.vhd) - write pump
- RDPUMP (swc_packet_mem_read_pump.vhd) - read pump
Each port has its own write and read pump. The pumps are an intermediate step (buffer)
between port (INPUT_BLOCK) and shared memory (FUCKING_BIG_MEMORY). Each pump has its own
time slot to access FUCKING_BIG_MEMORY. The time slot is one cycle. The time slot is
granted every 'c_swc_packet_mem_multiply' cycles (regardless it's requested by the pump or not).
** writing **
'c_swc_packet_mem_multiply' number of words written to a pump are saved in
FUCKING_BIG_MEMORY (when the access is granted). Writting to a pump can be done
regardless of the time slots granted to the pumps (at any time). It can be done as long as
the pump's buffer (register of c_swc_packet_mem_multiply words) is not full.
The address of the word is determined by the provided to the pump pgaddr
(page address, which comes from page allocator) and internal page address:
addres = pgaddr + inter_page_addr.
A page starts at the pgaddr, a page has c_swc_page_size number of inter_page_addres (words)
When the register which is currently being filled-in is going to be written to the
last word of the page, the rd_pageend_o is high indicating that next page needs to be allocated.
If the data which is written to a page by a port does not fill entire
input register (the number is not modulo c_swc_packet_mem_multiply), but
the port wants to write next data to new page and save in the FUCKING_BIG_MEMORY
the "not-full-input-reg", e.g. new package is to be saved, then wr_flush_i should be
set HIGH, it forces the pump to save "not-entirely-full" input register
in FUCKING_BIG_MEMORY during the next time slot for this port
** reading **
Similar to writing. there is a register of c_swc_packet_mem_multiply words
(ctrl+data) which are read from FUCKING_BIG_MEMORY in the pump's time slot (one cycle).
Each word of the register is made available consequtivelly, so first the
LSB word can be read by the port (availability of data is indicated by
rd_drdy_o being set to HIGH. Next word can be requested by setting rd_dreq_i
HIGH (while the previous word is read).
Speaking with the SWcore guts:
1) INPUT_BLOCKs (swc_input_block.vhd) - each block can write simultaneously to the
MUPTIPORT_MEMORY (the appripriate WRPUMP)
2) OUTPUT_BLOCKs (swc_output_block.vhd) - each block can read simultaneously from the
MUPTIPORT_MEMORY (the appripriate RDPUMP)
3) LINKED_LIST (swc_multiport_linked_list.vhd) - It stores the page addresses of packages
in a linked list. So you only need to know the address of the first page where
the package was stored. The addresses of the other pages are in a linked list:
the first address points to the second, the second to the third, etc... This linked
list is filled in when the MUPTIPORT_MEMORY is written to, and read when it is read from.
Internal components of the MUPTIPORT_MEMORY:
5.1 FUCKING_BIG_MEMORY (generic_ssram_dualport_singleclock.vhd)
This is a single SSRAM which is accessed by all the write/read pumps. It's very big, thus the name.
5.2 WRPUMP (swc_packet_mem_write_pump.vhd)
Collectes data (words of ctrl+data seq) from one port and
pumps (saves) sequence of such data to one word of SRAM memory with the
page address allocated by mutiport memory allocator. The access to
SSRAM is shared equally between many such pumps, each pump represents
one port.
A pump works in the following way:
1) it collects data from a port, data can be written continuously.
- data consits of a word of ctrl + data seq
- one word can be written at one clock cycle, in such case drdy_i is
- constantly HIGH
2) if entire "vector" of data words is collected ('c_swc_packet_mem_multiply'
number of data words), such a vector is written to SSRAM to one word:
- the dats is written to SRAM memory address = page_addr + offset
- each "memory page" (indicated by page_addr) consists of a few
SRAM consecutive addresses
3) when the vector to be written to the last address of the page is being
filled in, the 'pend_o' indicates that the end of the page
Each pump has its 'time slot' (one cycle) to read/write from/to
*FUCKING BIG SRAM (FB SRAM)*. The access is granted to each pump in sequence:
1,2,3...(c_swc_packet_mem_multiply - 1). The access is multiplexed
between the pumps.
If we want to write to the FUCKING BIG SRAM vector not fully filled in with data,
we can use 'flush_i'. High stribe on flush input enforces the pump to
behave as if it was full and the write to FB SRAM was needed in the
next available 'time slot'.
5.3 RDPUMP (swc_packet_mem_read_pump.vhd)
This piece of code reads a bunch ('c_swc_packet_mem_multiply'
of words = ctrl + data) from the FUCKING BIG SRAM and makes it available
for read by port. There is one read_pump for each port. Each pump has its
time slot to read from FB SRAM.
the thing works in the following way:
1) it takes the address (FB SRAM addr) of the page
2) it reads it in its time slot which is one cycle every
c_swc_packet_mem_multiply cycles
3) it makes it available on its output (d_o) word by word (in number of
c_swc_packet_mem_multiply words, this is how many words is saved in
on FB SRAM word)
4) it announces it with 'drdy_o' HIGH
5) the next word is available after setting dreq_i high
6. LINKED_LIST (swc_multiport_linked_list.vhd)
As the name says: it is a linked list !!!
The beginning of a list is the first page allocated to a given package (Ethernet Frame).
All the lists are stored in a single SSRAM (PAGE_INDEX_LINKED_LIST).
Since, each WR PUMP and RD PUMP needs to have access to the SSRAM with the linked list, the
access is govenred by a round robin arbiter (one for writing, on for reading).
Speaking with the SWcore guts:
1) MUPTIPORT_MEMORY (swc_packet_mem.vhd) - to be more precise, each WRPUMP and RDPUMP in
the multiport memory has individual access to the linked list.
2) PCK_PAGES_FREEEING_MODULE (swc_multiport_pck_pg_free_module.vhd) - it reads the addresses
of a package which has been successfully sent to all designated ports and the
memory (allocated pages) can be freed. You need to know the addresses of the pages to be
freed, so you read them from the linked list...
Internal components of the LINKED_LIST:
6.1 PAGE_INDEX_LINKED_LIST (generic_ssram_dualport_singleclock)
The SSRAM with the linked list. So under an address X in the SSRAM we have (as a data)
a page address Y. Under the address Y we have (as a data) the address Z, etc.
If the data is 0xF...F, it means the end of the list (last page allocated to a give package).
6.2 WRITE_ARB (swc_rr_arbiter.vhd)
It is a Round Robbin arbiter which grands access to the Linked List SSRAM.
The write access is shared between all the RDPUMPs in the MUPTIPORT_MEMORY
6.3 READ_ARB (swc_rr_arbiter.vhd)
It is a Round Robbin arbiter which grands access to the Linked List SSRAM.
The read access is shared between :
- all the RDPUMPS in the MUPTIPORT_MEMORY
- PCK_PAGES_FREEEING_MODULE
7. MEMORY_MANAGEMENT_UNIT (swc_multiport_page_allocator.vhd)
This module provides multi-access from many modues (INPUT_BLOCKs and PCK_PAGE_FREEING_MODULE)
to a single ALLOC_CORE which does the real work.
Speaking with the SWcore guts:
1) PCK_PAGES_FREEEING_MODULE (swc_multiport_pck_pg_free_module.vhd) - this module is responsible
for freeing pages, it is a proxy between modules which have the need to free pages and the
MEMORY_MANAGEMENT_UNIT
2) INPUT_BLOCK (swc_input_block.vhd) - each INPUT_BLOCK interfaces MEMORY_MANAGEMENT_UNIT
individually,
Internal components of the LINKED_LIST:
7.1 ALLOC_CORE (swc_page_allocator.vhd)
Module implements a fast (3 cycle) paged memory allocator.
The address of allocated page is made up of two parts:
* high: bits [x downto 5]
* low : bits [4 downto 0]
The low part of the page address (the low bits) is mapped to
a bit of 32 bit word in L0_LUT SRAM.
The high part of the page address is the address of the word in
the L0_LUT_SRAM memory. The address of the word in SRAM is
mapped into a bit of l1_bitmap register (high bits of the address).
Address mapped into bit means that the position of the bit (from LSB)
is equal to the address.
'1' means that a give address is free
'0' means that a give address is used
Tha page allocator looks for the lowest free (unused) page address. It uses
prio_encoder for this purpose.
prio_encoder's input is a bit vector, the output is the position of the
least significant bit set to '1' (see description of prio_encoder).
Additionally, prio_encoder returns the position encoded as one_hot and
a mask.
In the L0_UCNTMEM SRAM, the number of users assigned to a particular
page address is stored. the address in L0_UCNTMEM SRAM corresponds
directly to the page address. The default value to fill in the
SRAM are all '1s'.
The default value to fill in the l1_bitmap register is all '1s'.
Page allocation:
When page allocation is requested, the number of users (usecnt) needs
to be provided. The allocation of the page is not complited until
the provided number of users have read the page (attempted to free
the page). During allocation, the lowest free page address is sought.
As soon as the address is determined, the requested user count is
written to L0_UCNTMEM SRAM and allocation is finished.
Page Deallocation:
When free_page is attempted, the address of the page needs to be provided.
The address is decoded into high and low parts. First, the count in
L0_UCNTMEM SRAM is checked, if it's greater than 1, it is decreased.
If the usecount == 1, it means that this was the last page user, and thus
the page is freed. this means that '1' is written to the bit corresponding
to the page low part of the address in the word in L0_LUT SRAM. And '1' is
written to the l1_bitmap register to the bit corresponding to the high part
of the address.
7.2 ARB (swc_rr_arbiter.vhd)
This module makes everyone happy... it is a Round Robbin arbiter.
It arbits the access to ALLOC_CORE betwee:
- INPUT_BLOCKs
* page allocation
* forced page deallocation
* setting usecnt (based on the number of '1's in the port_mask vector
- PCK_PAGE_FREEING_MODULE
8. PCK_PAGES_FREEEING_MODULE (swc_multiport_pck_pg_free_module.vhd)
This is just a wrapper to instanciate port_number of LPDs (swc_pck_pg_free_module.vhd)
Speaking with the SWcore guts:
1) INPUT_BLOCK (swc_input_block.vhd) - input block makes requests to:
* allocate new pages
* set usecnt (now many times a page needs to be readout -> how many output_blocks need
to read a given page
* faoced freeing (if the package reception is dropped)
2) OUTPUT_BLOCK (swc_output_block.vhd) - it makes a request to free pages associated with
a package, it translates into:
* going through all the pages allocated to a give package (using the linked-list )
* making request to the MEMORY_MANAGEMENT_UNIT to free the page which can result in:
-> decreasing usecnt if it is still greater then 0
-> deallocating the page if usecnt == 0
3) MEMORY_MANAGEMENT_UNIT (swc_multiport_page_allocator.vhd) - making requests to free pages
4) LINKED_LIST (swc_multiport_linked_list.vhd) - finding out addresses of the pages
associated with a given package (Ethernet frame). The address of the first page of
the package is provided by the OUTPUT_BLOCK, but the rest of the addresses need to be
read from the Linked list
8.1 LPD (swc_pck_pg_free_module.vhd)
The incoming requests (to free or force_free pages) are inputed into a FIFO.
The main and only FSM reads the requests from the FIFO and executes them:
(1) requests MEMORY_MANAGEMENT_UNIT to free/force_free a page of a give address
(2) reads the addres of the next page from the Linked lists
(3) if the page is not the last page of the package (pgaddress != 0xF..F), go to (1)
and free the next page, otherwise...
(4) all the pages of a give pacakge have been freed (uscnt decremented or deallocated),
so the new request from the FIFO can be readout
documents/specifications/old/HDL/WRSW_endpoint_MAC/drawings/tx_path_timing.svg 0 → 100644
View file @ 46a712c9
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documents/specifications/old/HDL/WRSW_endpoint_MAC/endpoint_spec.txt 0 → 100644
View file @ 46a712c9
Switch endpoint spec
Tomasz Wlostowski, 2009/04/13
ver 0.0.1
--------------------------------------
TOC:
--------
0. Introduction
1. General idea
2. Block diagram
2.1. RX path
2.2. TX path
2.3. Endpoint controller
2.4. Generic parameters
3. Interface description
3.0. Common/miscellanous signals
3.1 PHY interface
3.2. Host (switch fabric) interface
3.3. RTI (Routing Table Interface).
3.4. Wishbone system bus
4. Registers
4.0. EPx_RST - Endpoint reset register
4.1. EPx_CTL - Endpoint control registers:
4.2. EPx_STAT - Endpoint status register
4.3. EPx_IER - Endpoint interrupt enable register
4.4. EPx_ISR - Endpoint interrupt status register
4.5. EPx_ACT_CTL - Endpoint statistics accounting control register
4.6. EPx_ACT_CNTR_xxx - Endpoint statistics counter register family
4.7. EPx_TX_TS_FIFO_STATUS - Endpoint TX timestamping block FIFO status register
4.8. EPx_TX_TS_FIFO_TAG - Endpoint TX timestamping unit frame tag register
4.9. EPx_TX_TS_FIFO_TSVAL - Endpoint TX timestamping unit timestamp value register
4.10. EPx_TX_LCR - TX Link Control Register value register
4.11. EPx_RX_LCR - RX Link Control Register value register
0. Introduction
I wrote part of this stuff being in hospital, drugged a little bit with analgesics. So, if you find this document stupid/crazy/immature, don't hestitate to give some feedback :) Also, let me apologize for the quality of diagrams, they were drawn on my laptop using touchpad. The diagrams show my personal vision of the design. You don't have to use the exact structure I've proposed, just try to keep the interfaces compatible with descriptions. If something is left unexplained, do it as you wish - or ask me if you have any doubts.
1. General idea
Switch endpoint block implements some functionality of typical Ethernet MAC + some WR-specific extensions, like timestamping, fragmentation and HP/SP frames. Frames are passed from/to Host (Switch Fabric Interface). The endpoint also performs initial frame header analysis, distinguishes HP, SP, fragmented/contiunation frames. Parsed header data is passed via RTI to Routing Table Unit.
2. Block diagram
The general block diagram is on fig.1. It can be split into 3 parts:
2.1. Upper part contains the RX path. It gets the raw data from PHY, decodes it, checks the alignment using both 8b10b decoder and PHY sync/pass line. Decoded data is then transferred to main switch clock (refclk_i) domain using clock alignment FIFO.
Then RX data is passed to RX deframer. Purpose of this block is to:
- decode (8b10b) data stream
- detect frame preambles, headers, CRCs
- check frame integrity (FCS, header CRC32 for HP)
- detect frame type: SP, HP, unicast, multicast, broadcast
- parse frame headers (extract src/dst address, ethertype, HP flags, VLAN id/priority) and pass the data to Routing Table Interface).
- timestamp received packets and pass the timestamp and source-port ID data to Switch Fabric i/f
There is also separate preamble detection block, operating in parallel to RX deframer in phy_rbclk_i clock domain. Its purpuse is to generate trigger signal for taking precise RX timestamps.
2.2. Lower part of image shows the TX path. Its purpose is to:
- take high-level frame data
- encapsulate it, calculate all necessary checksums, add preamble, SFDs, EPDs, optional carrier extension
- encode with 8b10b
- be able to interrupt frame currently being transmitted.
- timestamp certain packets and record the timestamps.
Output data stream is then eventually passed though clock alignment FIFO (of same structure as one in RX path) and 8b-10b encoded. TX alignment FIFO is optional, and it should be possible to enable/disable it in entity parametrs. In case of downlink endpoint we don't need it at all, as the PHY is clocked with refclk_i. Uplink PHYs may be clocked both using compensated REFCLK or with loopbacked RBCLK - in this case alignment logic is necessary.
Note for RX FIFO:
For nonsynchronous mode it should compensate for local/remote frequency difference (~64 bytes should be enough for that) and during inter-frame gap, RX framing logic should purge it to avoid overflows.
For sync mode it should ONLY compensate for phase shift between refclk_i and phy_rbclk_i, not introducing any excessive delay, as it may affect determinism of switch for HP frames.
2.3. Center part contains Wishbone bus slave allowing for access to endpoint registers and timestamping unit.
Timestamping unit gathers both RX and TX timestamps, using counter clocked by refclk_i. Timestamps are gathered upon detection of SFD in data stream. Timestamps should be taken on both refclk_i edges (or you can use counter running at 2*refclk_i freq - it's up to you to decide) - see drawing 2 for explanation.
2.4. Generic parameters
Only one :)
- TX_PATH_CLK_SOURCE: allowing for selection of clock for PHY transmit path between rbclk_i and refclk_i
3. Interface description
This section contains descriptions of interface signals.
3.0. Common/miscellanous signals
- refclk_i - 125 MHz reference clock input. Master clock for entire switch.
- refclk2_i - 62.5 MHz reference clock (refclk/2, phase-aligned). Master clock for host interface and Wishbones
- rst_n_i - global switch reset input (active low). Resets all endpoint logic
- rst_ts_n_i - ASYNCHRONOUS reset of endpoint's timestamp counter. Active low.
- pps_i - PPS signal input, synchronous to refclk_i. Rising edge resets timestamp counters.
3.1 PHY interface
Endpoint block should primarily support TLK1221 GbE PHY from Texas Instruments. As most fiber PHYs are quite similar to each other, it shouldn't be very difficult to port endpoint design to use another chip. PHY interface uses following signals: (for detailed documentation, see TLK1221 datasheet)
TEMPLATE: signal_name [bus range] <clock domain>, driven by: block - description
PHY TX path:
- phy_td_o [9:0] <refclk_i/phy_rbclk_i>, driven by: TX path 8b10b-encoder
PHY transmit data, 8b10b-encoded.
- phy_enable_o <refclk_i/phy_rbclk_i>, driven by: EPx_CTL register, bit PHY_EN
PHY enable signal, active high during normal PHY operation
- phy_syncen_o <refclk_i/phy_rbclk_i>, driven by: EPxCTL register, bit PHY_SYNCEN
PHY synchronization logic enable. High level enables internal comma detection and channel alignment stuff
in PHY. It should be held high during normal operation.
- phy_loopen_o <refclk_i/phy_rbclk_i>, driven by: EPxCTL register, bit PHY_LOOPEN
PHY loopback mode enable. Active high, normally should be driven low (used for testing/initialization
purposes)
- phy_prbsen_o <refclk_i/phy_rbclk_i>, driven by: EPxCTL register, bit PHY_PRBSEN
PHY pseudo-random bit sequence generator enable. Active high, normally should be driven low (used for
testing/initialization purposes)
PHY RX path:
- phy_rbclk_i <clock signal>, driven by: PHY RBCLK0 output
Byte clock recovered from received Ethernet data stream.
- phy_rd_i <phy_rbclk_i>, driven by: PHY RDx outputs
Received raw data stream, 8b10b-encoded, comma-aligned.
- phy_sync_pass_i <phy_rbclk_i (check the doc)>, driven by: PHY SYNC/PASS pin
PHY sync detect signal (see TLK1221 datasheet for details)
3.2. Host (switch fabric) interface
This interface connects the endpoint with switch fabric (commutation field) and packet buffer/scheduler logic.
RX path signals (all synchronous to refclk2_i):
- rx_enable_i, driven by: fabric i/f
'1' enables reception operation. When it's asserted high in the middle of the frame, endpoint should start reception operation with the next
incoming frame.
- rx_frame_stb_o, driven by: RX deframer
RX frame strobe signal, indicating beginning of reception of ethernet frame. It's asserted 1 for single
REFCLK cycle upon detection of valid preamble and SFD.
- rx_data_o [15:0], driven by: RX deframer
Received data bus. Outputs entire frame data, starting from DST MAC and ending with FCS value and
additional out-of-band data. To reduce the fabric clock for easier FPGA implementation, single clock cycle allows for transferring
two bytes of frame data. First byte is MSB, the second one - LSB.
- rx_data_bytesel_o, driven by: RX deframer
'1' Indicates single byte transfer on rx_data_o. May occur only at the end of block of data (e.g. frame, header, tag or OOB).
Transferred byte is the MSB of rx_data_o.
- rx_data_valid_o, driven by: RX deframer
'1' indicates that current byte on rx_data_o is valid frame byte.
- rx_hdr_begin_stb_o, driven by: RX deframer
RX header begin strobe signal. Asserted hi for one REFCLK cycle when the deframer detects beginning of frame header.
- rx_hdr_done_stb_o, driven by: RX deframer
RX header done strobe signal. Asserted hi for single REFCLK cycle after RX deframer has parsed frame
headers and outputted them to rx_data_o. Along with assertion of this signal, rx_is_hp_o, rx_hp_flags_o, rx_is_fragmented_o,
rx_is_frag_cont_o, rx_is_pause_o, rx_is_unicast_o, rx_is_multicast_o, rx_is_broadcast_o are set to proper
values. The data passed afterwards to rx_data_o is frame payload data.
- rx_oob_begin_stb_o, driven by: RX deframer
RX out-of-band data begin strobe signal. Asserted hi for one REFCLK cycle after all the frame payload data (with FCS)
has been outputted to rx_data_o bus and RX deframer is about to send source port ID and reception timestamp to Switch fabric i/f.
- rx_oob_done_stb_o, driven by: RX deframer
RX out-of-band data end strobe signal. Asserted hi for one REFCLK cycle upon sending source port ID and RX timestamp to rx_data_o.
- rx_done_stb_o, driven by: RX deframer
RX done strobe signal. Asserted hi for one REFCLK cycle upon reception of entire frame (with header/OOB data).
- rx_idle_o, driven by: RX deframer
RX path idle signal, active hi if RX path is not doing anything interesting (when it's receiving commas or
link idle pattern )
- rx_sync_o, driven by: RX deframer, sync detect logic
RX sync signal. Derived from phy_sync_pass_i and by checking correctness of phy_rd_i by 802.x-compliant
sync FSM. High state means link is synchronized. When de-synchronization occurs during frame reception,
operation is aborted and error code shall be issued. When rx_sync_o is low, RX deframer may not output any
data to fabric interface.
- rx_error_stb_o, driven by: RX deframer
RX error signal. Asserted hi for 1 REFCLK cycle along with rx_done_stb_o if an error has been
detected. Detection of error causes immediate abort of reception operation. Along with assertion of
rx_error_o, error code shall be output on rx_error_code_o.
- rx_error_code_o, driven by: RX deframer
RX error code. Asserted along with rx_error_o. Proposed error codes are below:
type t_mac_rx_error_code is std_logic_vector(3 downto 0);
constant c_RXERR_INVALID_CRC: t_mac_rx_error_code := "0000";
constant c_RXERR_ENCODING_ERROR: t_mac_rx_error_code := "0001";
constant c_RXERR_FRAME_TOO_LONG: t_mac_rx_error_code := "0010";,
constant c_RXERR_FRAME_TOO_SHORT: t_mac_rx_error_code := "0011";,
constant c_RXERR_INVALID_HEADER: t_mac_rx_error_code := "0100";
constant c_RXERR_GAP_VIOLATION: t_mac_rx_error_code := "0101";
constant c_RXERR_HP_HEADER_INVALID: t_mac_rx_error_code := "0110";
constant c_RXERR_LINK_OUT_OF_SYNC: t_mac_rx_error_code := "0111";
RX frametype signals:
- rx_is_hp_o, driven by: RX deframer
High state means that current frame contains valid HP header. It's asserted along with rx_hdr_done_stb_o.
- rx_hp_flags_o, driven by: RX deframer
Value of hp_flags field extracted from HP frame header.
- rx_is_fragmented_o, driven by: RX deframer
High state means that current frame has been fragmented (e.g. broken frame marker has been detected).
Signal is asserted along with rx_done_stb_o.
- rx_is_frag_cont_o, driven by: RX deframer
Hi state indicates that currently received frame contains SP frame continuation header. Asserted along with
rx_hdr_done_stb_o.
- rx_is_pause_o, driven by: RX deframer
Hi state indicates that we've just received PAUSE frame. Delay value extracted from frame shall be
outputted to rx_pause_count_o.
- rx_pause_count_o [15:0], driven by: RX deframer
Value of pause interval.
- rx_is_unicast_o: driven by: RX deframer
- rx_is_multicast_o: driven by: RX deframer
- rx_is_broadcast_o: driven by: RX deframer
'1' means that frame is unicast/multicast/broadcast frame. Asserted along with rx_hdr_done_stb_o.
TX path signals (all synchronous to refclk2_i)
- tx_data_i[15:0], driving: TX framer.
Transmit path data input. Should contain full frame data (WITHOUT preamble, SFD and FCS, which are added by TX framer).
- tx_data_bytesel_i, driving: TX framer.
'1' Indicates single-byte transfer on tx_data_i. Transmitted byte is placed on tx_data_i[15:8] (MSB).
- tx_enable_i, driving: TX framer, 8b10b encoder, etc.
TX path enable. Active high.
- tx_frame_stb_i, drives: TX framer.
RX frame strobe signal, Should be asserted for single REFCLK cycle in order to start transmission of the
frame. Upon assertion, TX framer begins transmission of preamble, SFD, headers. Frame data should be
supplied on tx_data_i when tx_input_ready goes high.
- tx_oob_begin_i, drives: TX framer
Single REFCLK-long '1' indicates beginning of out-of-band data for this frame (e.g. frame tag value).
- tx_oob_end_i, drives: TX framer
Single REFCLK-long '1' indicates end of out-of-band data for this frame (e.g. frame tag value).
- tx_input_ready_o: driven by: TX framer.
TX framer input ready - '1' means that TX framer is ready to accept data ib tx_data_i.
- tx_data_valid_i: driving TX framer.
TX input data byte valid. '1' means that byte currently transferred on tx_data_i is valid frame byte. Since TX framer contains small (~16
byte) FIFO, we can suspend frame data during frame transmission for few clock cycles by driving this signal low.
- tx_idle_o, driven by: TX framer.
Active '1' when TX framer is not transmitting anything. Goes '1' after transmission of the frame and 12-
byte inter-frame gap. Goes '0' upon assertion of tx_frame_stb_i.
- tx_is_hp_i, drives: TX framer.
Asserted with tx_frame_stb_i. '1' means that we want to transmit HP frame, bypassing FIFOs. HP frame data
shall be sent immediately when tx_input_ready goes high in single block.
- tx_preemptible_o, driven by: TX framer
Asserted '1' when frame is long enough (e.g. it fits the min. 64-byte requirement) to be fragmented.
When it's 0 you can only abort the frame and retransmit it later.
- tx_fragment_i, drives: TX framer.
Assertion '1' for single refclk_i cycle during frame transmission causes the frame to be fragmented.
TX framer should generate proper markers and CRC + IFG. TX framer should store necessary data
(previous fragment CRC and last transmitted byte offset).
- tx_continue_i, drives: TX framer.
Assertion '1' for single refclk_i cycle along with rx_frame_stb_i causes TX framer to generate continuation
SP frame. When tx_input_ready goes high, host interface should continue sending frame data starting at previous offset.
- tx_end_frame_i: drives TX framer.
Assertion '1' for single refclk_i cycle tells the TX framer that we're done sending frame data. TX framer
shall then generate proper CRC and IFG, then go idle.
- tx_send_pause_i: drives TX framer.
Assertion '1' for single refclk_i cycle along with rx_frame_stb_i causes TX framer to send 802.x PAUSE frame
with counter value supplied by tx_pause_count_i input.
- tx_pause_count_i[15:0]: drives TX framer.
Value of pause interval.
- tx_abort_i, drives: TX Framer.
TX abort input. Immediately aborts currently transmitted frame, with INVALID FCS.
- tx_error_stb_o, driven by: TX framer
TX error signal. Asserted hi for 1 REFCLK cycle if an error has been
detected. Detection of error causes immediate abort of transmit operation (generating frame with invalid FCS)
Along with assertion of tx_error_o, error code shall be output on tx_error_code_o.
- tx_error_code_o, driven by: TX framer
TX error code. Asserted along with tx_error_o. Proposed error codes are below:
type t_mac_tx_error_code is std_logic_vector(3 downto 0);
constant c_TXERR_LINK_OUT_OF_SYNC: t_mac_rx_error_code := "0000";
constant c_TXERR_BUFFER_UNDERRUN: t_mac_rx_error_code := "0001"; -- TX buffer underrun error (e.g. FIFO is empty in the middle of
-- transmission of the frame
3.3. RTI (Routing Table Interface).
This i/f is used by endpoints to send frame header data to Routing Table Unit. RTU then takes the decision
where (and sometimes, when) to send the frame. RTU contains independent port (with cache) for each RTI interface.
RTI signals (all synchronous to refclk_i)
- rti_idle_i, driven by: RTU
'1' means that RTU port is idle and ready to accept RTU request.
- rti_rq_begin_o, driven by: endpoint
Assertion '1' for single refclk_i cycle indicates beginning of new RTU request. After then, endpoint shall
send the parsed frame header data on rti_data_o and rti_field_o lines.
- rti_data_o [7:0], driven by: endpoint
- rti_field_o [6:0] , driven by: endpoint
RTU request data. rti_field_o contains address of current header field (e.g 0000 = 1st byte of
destination MAC, 1000 = first byte of SRC mac, etc....), rti_data_o contains the value.
- rti_data_valid_o, driven by: endpoint
'1' indicates that current data on rti_data_o and rti_field_o is valid.
- rti_rq_done_o, driven by: endpoint
Assertion '1' for single refclk_i cycle indicates an end of RTU request. After some clock cycles RTU shall
respond with routing decision.
3.4. Wishbone system bus
Wishbone bus is used for accessing endpoint register. It's a
standard Wishbone interface with two interrupt lines. WB bus is
synchronous to refclk2_i.
Additional IRQ lines:
- sys_irq_o: '1' indicates pending interrupt request.
- sys_irq_ack_i: '1' indicates that interrupt controller has received the interrupt request. When endpoint
sees this signal asserted, it shall de-assert it's sys_irq_o output.
4. Registers.
There is no strict register map. Detailed addresses and bit offsets have to be agreed between H/W module designer and driver developer.
My proposal is following:
4.0. EPx_RST - Endpoint reset register
(w/o) Writing anything to EPx_RST register causes immediate software reset of all endpoint logic.
4.1. EPx_CTL - Endpoint control registers:
Bit fields:
(r/w) EPCTL_ENABLE - enable TX/RX path (active 1, value '0' overrides fabric i/f signals tx_enable_i and rx_enable_i)
(r/w) EPCTL_PHYEN, EPx_SYNCEN, EPx_PRBSEN, EPx_LOOPEN - PHY control signals (GPIO)
(r/w) EPCTL_TX_CARRIER_EXT_EN - '1' enables carrier extension feature for transmitted frames
(r/w) EPCTL_RX_JUMBO_EN - enable reception of jumbo frames (e.g. > 1518-byte frame length will not cause an error)
(r/w) EPCTL_RX_RUNT_EN - enable reception of runt frames (e.g. < 64-byte frame length will not cause an error)
(r/w) EPCTL_RX_FIFO_PURGE - writing 1 immediately purges clock alignment FIFOs.
(w/o) EPCTL_LCR_SEND_EN - writing '1' causes EPx_TX_LCR register to be sent to remote endpoint using 802.x Send Config Register pattern. EPSTAT_LCR_SENT bit must be cleared. Upon transmission, EPSTAT_LCR_SENT bit is set to '1'.
(w/o) EPCTL_LCR_RECV_EN - writing '1' enables reception of LCR register. EPSTAT_LCR_RCVD bit must be cleared. The received value is stored in EPx_RX_LCR register. After then, EPSTAT_LCR_RCVD bit is set to '1'.
(r/w) EPCTL_TX_TS_EN - writing '1' enables TX packet timestamping. Packets are timestamped only if OOB block is present at the beginning of TX frame.
(r/w) EPCTL_RX_TS_EN - writing '1' enables RX packet timestamping. When enabled, OOB block is appended to RXed frame.
4.2. EPx_STAT - Endpoint status register
Bit fields:
(r/o) EPSTAT_SYNCED - link is initialized and synchronized (active 1)
(r/o) EPSTAT_CARRIER - carrier is present (active 1)
(r/o) EPSTAT_SYNCMODE - clock sync detected (probably we have synchronous mode, active 1)
(r/w) EPSTAT_LCR_SENT - Link Control Register has been sent. Writing '1' clears this bit.
(r/w) EPSTAT_LCR_RCVD - Link Control Register has been received. Writing '1' clears this bit.
4.3. EPx_IER - Endpoint interrupt enable register
Bit fields:
(r/w) EPSTAT_IRQ_LINK - link status changed interrupt (active 1, write 1 to clear)
(r/w) EPSTAT_IRQ_TX_TS - TX timestamp gathered interrupt
4.4. EPx_ISR - Endpoint interrupt status register
Bit fields:
(r/w) EPSTAT_IRQ_LINK - link status changed interrupt stauts, active '1'. Writing '1' clears the flag and acknowledges the interrupt.
(r/w) EPSTAT_IRQ_TX_TS - TX timestamp gathered interrupt, active '1'. Writing '1' clears the flag and acknowledges the interrupt.
4.5. EPx_ACT_CTL - Endpoint statistics accounting control register
Bit fields:
EPCTL_ACT_RXERR_RST
EPCTL_ACT_TXERR_RST
EPCTL_ACT_FRAG_RST
EPCTL_ACT_HP_DROP_RST
EPCTL_ACT_HP_COLLIDE_RST ^^^^^^^^^^^^^^^^^
EPCTL_ACT_FRAG_COUNT_RST - writing '1' to these bits causes reset of respective event counters
4.6. EPx_ACT_CNTR_xxx - Endpoint statistics counter register family
Registers:
EPx_ACT_RXERR_CNT - number of packets received with errors
EPx_ACT_TXERR_CNT - number of packets transmitted with errors (e.g. aborted, buffer underruns, etc)
EPx_ACT_FRAG_CNT - number of fragmentation events
EPx_ACT_HP_DROP_CNT - number of dropped HP frames
EPx_ACT_HP_COLLIDE_CNT - number of HP collisions detected
EPx_ACT_FRAG_COUNT_RST - max. number of fragments of single frame transmitted by endpoint.
4.7. EPx_TX_TS_FIFO_STATUS - Endpoint TX timestamping block FIFO status register
Bit fields:
(r/o) EPx_TX_TS_FIFO_COUNT[4:0] - amount of timestamps in FIFO.
(w/o) EPx_TX_TS_FIFO_ADVANCE - writing '1' causes advancing to next gathered timestamp in FIFO. It's data will be available in TAG and TSVAL registers.
4.8. EPx_TX_TS_FIFO_TAG - Endpoint TX timestamping unit frame tag register. Contains tag value from OOB block of timestamped frame.
4.9. EPx_TX_TS_FIFO_TSVAL - Endpoint TX timestamping unit timestamp value register. Contains timestamp coutnter value of frame with tag stored in EPx_TX_TS_FIFO_TAG register.
In order to read TX timestamps, CPU has to.
- check EPx_TX_TS_FIFO_STATUS reg to determine if any frames have been timestamped.
- read TAG and TSVAL registers.
- write '1' to TS_FIFO_ADVANCE bit in order to proceed to next tag-timestamp pair.
For detailed description, see the Timestamping Architecture document.
4.10. EPx_TX_LCR - TX Link Control Register value register
Bit fields:
(r/w) EPx_TX_LCR_VAL[15:0] - Contains value of LCR register to be sent during 802.x link negotiation procedure.
4.11. EPx_RX_LCR - RX Link Control Register value register
Bit fields:
(r/o) EPx_RX_LCR_VAL[15:0] - Contains value of LCR register received from remote endpoint during 802.x link negotiation procedure.
documents/specifications/old/HDL/WR_Fabric_IF/src/fabric_link.svg 0 → 100644
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documents/specifications/old/HDL/WR_Fabric_IF/src/fabric_sample_xfer.svg 0 → 100644
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