Commit fb415263 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

docs/specs/HDL/WRS_HDL-SW_IF: use common figures

parent 5bd39806
all : switch_hdl.pdf
.PHONY : all clean
switch_hdl.pdf : switch_hdl.tex
latex $^
latex $^
dvips switch_hdl
ps2pdf switch_hdl.ps
clean :
rm -f *.eps *.pdf *.dat *.log *.out *.aux *.dvi *.ps *.toc
all:
wbgen2 -f latex -D wrsw_endpoint.tex wbgen/ep_wishbone_controller.wb
wbgen2 -f latex -D i2c_master.tex wbgen/i2c_master.wb
wbgen2 -f latex -D wrsw_endpoint_mdio.tex wbgen/pcs_regs.wb
wbgen2 -f latex -D wr_pps_gen.tex wbgen/pps_gen_wb.wb
wbgen2 -f latex -D wb_simple_uart.tex wbgen/simple_uart_wb.wb
wbgen2 -f latex -D wb_gpio.tex wbgen/wb_gpio.wb
wbgen2 -f latex -D wb_vic.tex wbgen/wb_slave_vic.wb
wbgen2 -f latex -D wrsw_nic.tex wbgen/wr_nic.wb
wbgen2 -f latex -D wrsw_pstats.tex wbgen/wrsw_pstats.wb
wbgen2 -f latex -D wrsw_rtu.tex wbgen/wrsw_rtu.wb
wbgen2 -f latex -D wrsw_txtsu.tex wbgen/wrsw_txtsu.wb
wbgen2 -f latex -D wrsw_tru.tex wbgen/tru_wishbone_slave.wb
wbgen2 -f latex -D wrsw_tatsu.tex wbgen/tatsu_wishbone_controller.wb
wbgen2 -f latex -D wb_simple_pwm.tex wbgen/simple_pwm_wb.wb
wbgen2 -f latex -D wrsw_hwiu.tex wbgen/wrsw_hwiu.wb
This diff is collapsed.
\subsection{Wishbone GPIO}
\label{subsec:wbgen:gpio}
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{RoyalPurple}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x0& REG & Clear Output Register & gpio\_codr & CODR\\
0x4& REG & Set Output Register & gpio\_sodr & SODR\\
0x8& REG & Data Direction Register & gpio\_ddr & DDR\\
0xc& REG & Pin State Register & gpio\_psr & PSR\\
\hline
\end{tabular}
}
\subsubsection{Register description}
\paragraph*{Clear Output Register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & gpio\_codr\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & CODR\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\vspace{12pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CODR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CODR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CODR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CODR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CODR
} [\emph{write-only}]: Clear GPIO outputs
\\
Each bit corresponds to one GPIO line \\ write 1 to bit n: clear n-th line \\ write 0: no effect
\end{small}
\end{itemize}
\paragraph*{Set Output Register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & gpio\_sodr\\
{\bf HW address:} & 0x1\\
{\bf SW prefix:} & SODR\\
{\bf SW offset:} & 0x4\\
\end{tabular}
\vspace{12pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SODR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SODR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SODR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SODR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
SODR
} [\emph{write-only}]: Set GPIO outputs
\\
Each bit corresponds to one GPIO line \\ write 1 to bit n: set n-th line to 1\\ write 0: no effect
\end{small}
\end{itemize}
\paragraph*{Data Direction Register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & gpio\_ddr\\
{\bf HW address:} & 0x2\\
{\bf SW prefix:} & DDR\\
{\bf SW offset:} & 0x8\\
\end{tabular}
\vspace{12pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DDR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DDR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DDR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DDR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DDR
} [\emph{read/write}]: GPIO direction
\\
Each bit corresponds to one GPIO line \\ 1: n-th line is output \\ 0: n-th line is input
\end{small}
\end{itemize}
\paragraph*{Pin State Register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & gpio\_psr\\
{\bf HW address:} & 0x3\\
{\bf SW prefix:} & PSR\\
{\bf SW offset:} & 0xc\\
\end{tabular}
\vspace{12pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}PSR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}PSR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}PSR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}PSR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
PSR
} [\emph{read-only}]: Read GPIO inputs
\\
Each bit corresponds to one GPIO line \\ read: current status of n-th input
\end{small}
\end{itemize}
\subsection{Simple Wishbone UART}
\label{subsec:wbgen:uart}
A simple Wishbone UART (8N1 mode) with programmable baud rate.
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{RoyalPurple}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x0& REG & Status Register & uart\_sr & SR\\
0x4& REG & Baudrate control register & uart\_bcr & BCR\\
0x8& REG & Transmit data regsiter & uart\_tdr & TDR\\
0xc& REG & Receive data regsiter & uart\_rdr & RDR\\
0x10& REG & Host VUART Tx register & uart\_host\_tdr & HOST\_TDR\\
0x14& REG & Host VUART Rx register & uart\_host\_rdr & HOST\_RDR\\
\hline
\end{tabular}
}
\subsubsection{Register description}
\paragraph*{Status Register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & uart\_sr\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & SR\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RX\_RDY} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}TX\_BUSY}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TX\_BUSY
} [\emph{read-only}]: TX busy
\\
1: UART is busy transmitting a byte\\0: UART is idle and ready to transmit next byte
\end{small}
\item \begin{small}
{\bf
RX\_RDY
} [\emph{read-only}]: RX ready
\\
1: UART received a byte and its in RXD register\\0: no data in RXD register
\end{small}
\end{itemize}
\paragraph*{Baudrate control register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & uart\_bcr\\
{\bf HW address:} & 0x1\\
{\bf SW prefix:} & BCR\\
{\bf SW offset:} & 0x4\\
\end{tabular}
\vspace{12pt}
Register controlling the UART baudrate
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BCR
} [\emph{write-only}]: Baudrate divider setting
\\
Baudrate setting. The value can be calculated using the following equation:\\ BRATE = ((Baudrate * 8) << 9 + (ClockFreq >> 8)) / (ClockFreq >> 7)
\end{small}
\end{itemize}
\paragraph*{Transmit data regsiter}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & uart\_tdr\\
{\bf HW address:} & 0x2\\
{\bf SW prefix:} & TDR\\
{\bf SW offset:} & 0x8\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TX\_DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TX\_DATA
} [\emph{write-only}]: Transmit data
\end{small}
\end{itemize}
\paragraph*{Receive data regsiter}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & uart\_rdr\\
{\bf HW address:} & 0x3\\
{\bf SW prefix:} & RDR\\
{\bf SW offset:} & 0xc\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}RX\_DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
RX\_DATA
} [\emph{read-only}]: Received data
\end{small}
\end{itemize}
\paragraph*{Host VUART Tx register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & uart\_host\_tdr\\
{\bf HW address:} & 0x4\\
{\bf SW prefix:} & HOST\_TDR\\
{\bf SW offset:} & 0x10\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RDY}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DATA
} [\emph{write-only}]: TX Data
\end{small}
\item \begin{small}
{\bf
RDY
} [\emph{read-only}]: TX Ready
\end{small}
\end{itemize}
\paragraph*{Host VUART Rx register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & uart\_host\_rdr\\
{\bf HW address:} & 0x5\\
{\bf SW prefix:} & HOST\_RDR\\
{\bf SW offset:} & 0x14\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}COUNT[15:15]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}COUNT[14:7]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{7}{|c|}{\cellcolor{RoyalPurple!25}COUNT[6:0]} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RDY}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DATA
} [\emph{read-only}]: RX Data
\end{small}
\item \begin{small}
{\bf
RDY
} [\emph{read-only}]: RX Ready
\end{small}
\item \begin{small}
{\bf
COUNT
} [\emph{read-only}]: RX FIFO Count
\end{small}
\end{itemize}
This diff is collapsed.
This diff is collapsed.
top = peripheral {
name = "Wishbone I2C Master";
hdl_entity = "i2c_wishbone_slave";
prefix = "i2c";
reg {
name = "Clock prescale register LSB";
prefix = "prer_lsb";
field {
name = "Clock prescale LSB";
description = "Bits 7:0 of 16-bit PRER register";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
}
};
reg {
name = "Clock prescale register MSB";
prefix = "prer_msb";
field {
name = "Clock prescale MSB";
description = "Bits 15:8 of 16-bit PRER register. Register stores the prescale value for SCL clock \
scl_clk = clk_sys / (5* PRER) \
a new value can be stored only when the module is disabled (CTR register)";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
}
};
reg {
name = "Control register";
prefix = "ctr";
field {
name = "reserved";
prefix = "rsv";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Interrupt enable";
prefix = "ien";
description = "Enable interrupt generation \
1: interrupt enabled \
0: interrupt disabled";
size = 1;
align = 6;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Enable module";
prefix = "en";
description = "1: module enabled \
0: module disabled";
size = 1;
align = 7;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
}
};
reg {
name = "Transmit/Receive register";
prefix = "txrx";
field {
name = "value";
description = "write: byte to be transmitted to i2c bus \
read: byte received from i2c bus";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Command/Status register";
prefix = "crsr";
field {
name = "value";
description = " write: \
bit 7: generate (repeat) start condition \
bit 6: generate stop consitoin \
bit 5: read from slave \
bit 4: write to slave \
bit 3: if 0, send ACK; if 1, send NACK \
bit 0: acknowledge interrupt \
read: \
bit 7: if 0, received ACK; if 1, no ACK received \
bit 6: i2c bus busy \
bit 5: i2c bus arbitration lost \
bit 1: transfer in progress \
bit 0: interrupt pending";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Interface select register";
prefix = "ifs";
field {
name = "I2C i/f number";
prefix = "if_num";
description = "select I2C interface: \
0: MiniBackplane 0 \
1: MiniBackplane 1 \
2: Sensors I2C";
size = 4;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {