... | ... | @@ -23,8 +23,8 @@ slave mode, WRPC receives the timing information from a PTP master, |
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synchronizes its internal clock and provides the timing information for
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other IP cores through a simple VHDL interface.
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This page briefly describes the hardware requirements to integrate the
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WRPC into two projects: Upgrading an existing system with WRPC and
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This wiki page briefly describes the hardware requirements to integrate
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the WRPC into two projects: Upgrading an existing system with WRPC and
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building a compact embedded solution.
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... | ... | @@ -33,9 +33,9 @@ building a compact embedded solution. |
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Only a few additional components are required to upgrade an existing
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system with the WRPC, presuming the existing project already includes an
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appropriate FPGA and the required environment (power supply,
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appropriate FPGA and the required environmental hardware (power supply,
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configuration etc.). WRPC has been successfully tested with GTP and GTX
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transceivers of Xilinx's FPGAs (e.g. Spartan-6 LXT family). Support for
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transceivers of Xilinx's FPGAs (e.g. Spartan-6 LXT family), support for
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Altera GX PHYs is currently being implemented.
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The drawing below depicts the necessary external components to upgrade
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... | ... | @@ -83,7 +83,7 @@ Scheduled features may include: |
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- Single supply operation (e.g. +12 V input, DC/DC converters onboard)
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- Inputs / outputs for PPS and external frequency
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- FLASH configuration memory
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- Master / slave operation jumper-selectable
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- Master / slave operation selectable by jumper (multiboot)
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- MAC address allocation TBD
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