| ... | ... | @@ -53,17 +53,20 @@ for every budget and taste. |
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Intro (Javier)
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WR switch hardware status (7sols and Tom)
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WR switch software status (Alessandro and Integrasys)
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WR switch software status and roadmap (Alessandro, Tom, Greg D.,
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Maciej)
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WR Standardization (Maciej)
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Etherbone status
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The GSI timing kit
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WR for KM3Net (Henk and Peter)
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The WR NIC reference design (Alessandro and 7sols)
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PPSi status (Aurelio)
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WR at DESY: The HiSCORE WR installation; ideas for CTA (Martin)
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WR at DESY: The HiSCORE WR installation; ideas for CTA (Martin)
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WR switch 802.1q functional test results (Integrasys)
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## Participants so far
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Miguel Baizán (Integrasys)
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Dietrich Beck (GSI)
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Bartosz Bielawski (CERN)
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Martin Brückner (Humboldt University Berlin)
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| ... | ... | @@ -74,9 +77,13 @@ Paloma Dorado (CDTI) |
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Mesfin Gebyehu (NIKHEF)
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Peter Jansweijer (NIKHEF)
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Maciej Lipiński (CERN)
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Juan Luis Mañas (Integrasys)
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Juan Manuel Martínez (Integrasys)
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Henk Peek (NIKHEF)
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Diego Real (IFIC Valencia)
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Alessandro Rubini (GNUDD)
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Álvaro Sánchez (Integrasys)
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Juan Carlos Sánchez (Integrasys)
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Javier Serrano (CERN)
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Erik van der Bij (CERN)
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Ralf Wischnewski (DESY)
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| ... | ... | |
