... | ... | @@ -251,8 +251,25 @@ about the code layout of the WR Switch in the [Building and flashing |
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manual for v4.0
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release](https://www.ohwr.org/project/white-rabbit/uploads/d9f33d5629092f4453ddd4b310297b9a/wr-switch-sw-v4.0_build.pdf)
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??Author: Grzegorz Daniluk,
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[CERN](http://cern.ch??)
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??Author: Grzegorz Daniluk, [CERN](http://cern.ch??)
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-----
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## Building firmware
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### Q: It takes very long to synthesize.
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A: Yes, 18-port switch is a big complex design. If you want to speed up
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your development you can synthesize the 8-port version of the gateware
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to test new functionality. In that case you should make your synthesis
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inside *syn/scb\_8ports/*
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### Q: ISE appears to have frozen during MAP/PAR.
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A: Did you install a 64-bit version of ISE? It needs up to 4 GB of free
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RAM during mapping/routing the design. 32-bit version can't use more
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than 3 GBs and sometimes freezes instead of throwing an
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error.
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