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# Compact Universal Timing Endpoint Based on WR
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The Cute-WR project aims to build a self-contained White Rabbit Node implementation on a FPGA Mezzanine Card. The idea is to have a compact, low-cost and
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common WR node for synchronous DAQ frontends and other applications\!
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After ten years development, several generations of Cute-WR cards have been built. A short [introduction](https://ohwr.org/project/white-rabbit/wikis/uploads/c04c50234c7d16918538a7ef920ac4c3/journey_of_CUTE-WR.pdf) about the Cute-WR series and their application has been given on the 13th WR workshop.
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|**Version**|**Description**|**Status**|
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|----|----|----|
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|[Cute-WR](https://www.ohwr.org/project/cute-wr/wiki)|the first generation with Spartan6 FPGA|obsolete|
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|[Cute-WR-DP](https://www.ohwr.org/project/cute-wr-dp/wiki)|Dual port version of Cute-WR with Spartan6 FPGA|obsolete|
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|[Cute-WR-A7](https://www.ohwr.org/project/cute-wr-a7/wiki)|Dual port version with Artix7 FPGA|Active|
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|Cute-WR-A7-Lite|Single port, low cost version with Artix7 FPGA|Active|
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