Bug in the WB Master interface
The Wishbone Master interface, inside the WB serializer, it does not
write some locations of memory randomly. The address in the WB bus is
not incremented correctly.
The following image shows the test done:
We are writing data from the VME bus to the WB slave memory in the A_FPGA (green path).
The problem can be seen only if the clock frequency used in the A_FPGA's WB clock domain is low (eg. 15 MHz).
The following image shows the problem seen by accessing the board from remote position:
Now let's take a look to the WB bus in the A_FPGA with Chipscope:
It is possible to see that the address is not incremented properly.