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# Frequently Asked Questions Wishbone Serializer Core
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## Design
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### Q: I see that the project is "On Hold". What does that mean?
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Indeed, the project is "On Hold" as we believe it is not needed more for
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the projects that our section is responsible for. The design was meant
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to be used on the [VFC FMC
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carrier](https://www.ohwr.org/project/fmc-vme-carrier/wiki), but people
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writing VHDL for this board have already other solutions. Our section
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will develop applications instead for the [SVEC FMC
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carrier](https://www.ohwr.org/project/svec/wiki) that does not need any
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Wishbone communication between two FPGA's.
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The Wishbone Serializer core is in a working state, but still has a bug
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that seems to appear only when the clocks on both sides differ largely
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in frequency. This is documented in
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[Issue 623](https://www.ohwr.org/project/wb-serializer-core/issues/2).
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### Q: Are the reset signals asserted low or high?
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A: The rst\_i is asserted low. The gt\_reset\_in\_i is asserted
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high.
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## Synthesis
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### Q: Inside the WB serializer core, the "after" construct is widely used. Is it synthesizable?
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... | ... | @@ -11,13 +34,7 @@ clock's rising edge. The waveform will be clearer |
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but it is better not mixing constructs for simulation and constructs for
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synthesis.
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h2 Design
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### Q: Are the reset signals asserted low or high?
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A: The rst\_i is asserted low. The gt\_reset\_in\_i is asserted high.
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-----
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1 November 2012
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21 December 2012
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