... | ... | @@ -20,10 +20,10 @@ Projects](https://www.ohwr.org/project/fmc-projects). |
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*to be revised**
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- 2 Spartan6 FPGA
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o One dedicated to system tasks (S-FPGA)
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o One fully available for the user applications (A-FPGA)
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- 1 Analog Devices Sharc DSP
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- 2 Virtex 5 FPGA (XC5VLX110T-1FF1136)
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o One dedicated to system tasks (Main)
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o One fully available for the user applications (FMC)
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- 1 Analog Devices Sharc DSP (ADSP-21-369KBPZ-3A)
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- 2 HPC (High Pin Count) FMC slots
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- 40 user defined single ended (20 LVDS) connections from the A-FPGA
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to P2 available for rear plug-in units (transition modules)
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... | ... | @@ -35,14 +35,9 @@ Projects](https://www.ohwr.org/project/fmc-projects). |
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o 3 Phase Locked Loop (PLL) chips for clock cleaning and
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redistribution to the FPGAs and the pluggable modules
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- Large amount of on board memory
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o 2 completely independent 72Mbit ZBT SRAMS
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o A 2Gbit DDR3
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o 2 SPI 128Mbit flash proms for multiboot S-FPGA powerup
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configuration, storage of the A-FPGA firmware or of critical data
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o 2 SRAMS
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- Front panel connectivity
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o 2 Small Formfactor Pluggable (SFP)
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o 4 lemos configurable in all possible input/output combinations
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o 1 e-SATA (to be confirmed)
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o 1 e-SATA (RF Clock and Tag)
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-----
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... | ... | @@ -59,8 +54,12 @@ Projects](https://www.ohwr.org/project/fmc-projects). |
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>10-05-2010</td>
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<td>First specifications ready.</td>
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</tr>
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<tr class="odd">
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<td>13-09-2010</td>
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<td>Start of project. Design will partially be based on the [VME FMC carrier](https://www.ohwr.org/project/fmc-vme-carrier).</td>
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<td>Start of design. Design will partially be based on the [VME FMC carrier](https://www.ohwr.org/project/fmc-vme-carrier).</td>
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</tr>
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</tbody>
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</table>
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... | ... | |