... | ... | @@ -18,24 +18,21 @@ Projects](https://www.ohwr.org/project/fmc-projects). |
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## Main Features
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*to be revised**
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- 2 Virtex 5 FPGA (XC5VLX110T-1FF1136)
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o One dedicated to system tasks (Main)
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o One fully available for the user applications (FMC)
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o One fully available for the user applications (FMC)
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o Intercommunication between with Wishbone and dedicated gigabit
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connections
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- 1 Analog Devices Sharc DSP (ADSP-21-369KBPZ-3A)
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- 2 HPC (High Pin Count) FMC slots
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- 40 user defined single ended (20 LVDS) connections from the A-FPGA
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- 2 HPC (High Pin Count) FMC slots
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o 160 user signals on each FMC slot
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- 52 user defined single ended (20 LVDS) connections from the A-FPGA
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to P2 available for rear plug-in units (transition modules)
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- flexible clocking resources
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o 1 Voltage Controlled Temperature Compensated Crystal Oscillator
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(VCTCXO)
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o 1 any rate I2C programmable crystal oscillator
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o 1 Direct Digital Synthesizer (DDS)
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o 3 Phase Locked Loop (PLL) chips for clock cleaning and
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redistribution to the FPGAs and the pluggable modules
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- Flexible clocking resources
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o 200 MHz LVPECL high-stability oscillator
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o 1 clock distribution and division (Analog Devices)
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- Large amount of on board memory
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o 2 SRAMS
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o 2 SRAMS (32 Mbit each)
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- Front panel connectivity
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o 1 e-SATA (RF Clock and Tag)
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