... | ... | @@ -40,7 +40,7 @@ Projects](https://www.ohwr.org/project/fmc-projects). |
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Devices)
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o A front panel RF clock distribution to both FPGAs like above.
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- Large amount of on board memory
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o 2 SRAMS (32 Mbit each)
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o 2 SRAMS (4 M x 18 bit each)
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- Front panel connectivity
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o 1 e-SATA (RF Clock and
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Tag)
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