... | ... | @@ -25,12 +25,16 @@ Projects](https://www.ohwr.org/project/fmc-projects). |
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connections
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- 1 Analog Devices Sharc DSP (ADSP-21-369KBPZ-3A)
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- 2 HPC (High Pin Count) FMC slots
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o 160 user signals on each FMC slot
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- 52 user defined single ended (20 LVDS) connections from the A-FPGA
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to P2 available for rear plug-in units (transition modules)
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o 160 user signals on each FMC slot
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o 4 full-duplex giga-bit connections to each FMC slot
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- 16 Timing in and outputs from the Main FPGA to P2 to enable a
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physical timing interface via rear plug-in units (transition
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modules)
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- Flexible clocking resources
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o 200 MHz LVPECL high-stability oscillator
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o 1 clock distribution and division (Analog Devices)
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o 200 MHz LVPECL high-stability oscillator distributed through a
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programmable, low-jitter, clock distribution and division (Analog
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Devices)
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o A front panel RF clock distribution to both FPGAs like above.
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- Large amount of on board memory
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o 2 SRAMS (32 Mbit each)
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- Front panel connectivity
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