The VME64x core implements a VME64 slave on one side and a WishBone
master on the other without FIFOs in-between.
The core supports SINGLE, BLT (D32), MBLT (D64) and 2eSST transfers in A24 and A32
address modes and D08 (OE), D16, D32 data transfers. The core can be
configured via implemented CR/CSR configuration space. A ROACK type IRQ
controller with one interrupt input and a programmable interrupt level
and Status/ID register is provided.