VME64x to Wishbone Core
Project description
The VME64x core implements a VME64 slave on one side and a WishBone master on the other without FIFOs in-between.
The core supports SINGLE, BLT (D32), MBLT (D64) and 2eSST transfers in A24 and A32 address modes and D08 (OE), D16, D32 data transfers. The core can be configured via implemented CR/CSR configuration space. A ROACK type IRQ controller with one interrupt input and a programmable interrupt level and Status/ID register is provided.
If you're looking for a VME-bus master, see the project PCI-Express to VME bridge.
Main features
- VME64x slave
- CR/CSR space
- ROACK type IRQ controller with one interrupt input and a programmable interrupt level and Status/ID register
- Supported VME access modes
- SINGLE, BLT (D32), MBLT (D64), 2eSST (D64 - read only)
- A24 and A32 address modes and D08 (OE), D16, D32 data transfers
- WishBone master (user side)
- Pipelined/Non-pipelined WB master.
- Performances:
- User read > 80MB/s using 2eSST mode, peak read > 160MB/s (See performances)
Project information
Documents
- Wishbone System-on-chip (SoC) Interconnection Architecture for Portable IP Cores, Revision B4
- VME64 ANSI/VITA 1 1994
- VME64 Extensions ANSI/VITA 1.1 1997
- ANSI/VITA 1.5-2003 2eSST
Contacts
General question about project
- Tristan Gingold - CERN
- Erik van der Bij - CERN
Project Status
Date | Event |
---|---|
01-04-2010 | Start working on project. |
25-05-2010 | First HDL release. |
10-02-2011 | First register read/write made with the core on the VFC. |
01-02-2012 | New student will work full time on project. |
03-05-2012 | Core has been modified to implement CSR space. CSR and single R/W working on VFC V2. |
10-05-2012 | Working on BLT, MBLT and 2eSST implementation. |
06-06-2012 | Added data swap modes. A64, 2eVME and 2eSST not yet implemented. Independent tester added to team. |
30-07-2012 | SINGLE, BLT (D32), MBLT (D64) transfers in A16, A24, A32 and A64 address modes working on VFC V2 and SVEC V0. A ROACK type IRQ Controller is provided. |
30-11-2012 | Student Davide Pedretti left CERN. Thesis available. Core works. |
07-03-2013 | Several bugs found and corrected. Core is working, but needs a good review. |
01-07-2013 | Migrated the repository to Git. |
29-05-2013 | Core re-used as basis for design at GSI. |
29-11-2013 | Bug multiple cards DTACKing on same CSR address found. |
11-12-2013 | Decided to start in 2014 a new project to rewrite/cleanup the core to make it better maintainable. |
20-10-2014 | Project in same state as in 2013 and used reliably in many places. |
20-10-2014 | Found issue with WB error handling. |
12-01-2017 | Tom Levens working on a clean-up of the VME64x core in order to reduce the footprint and fix open issues. |
01-09-2017 | Tristan Gingold started to work on it to make the module more usable and maintainable. |
02-10-2017 | Work completed. |
14-12-2017 | Release 2.0 |
14-11-2019 | Add support for d16 only masters |
24-04-2019 | Release 2.1 with prefetching for MBLT reads |
05-10-2019 | Add performances |
11 July 2022