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We will also be happy to receive feedback from you when you'll dig into
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the code.
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May 2017: the core is still used for any design using the SVEC. You may
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follow any [outstanding
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issues](https://www.ohwr.org/project/vme64x-core/issues) (that don't
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stop us from using this core).
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-----
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## Technical
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This is the default setup in `VME_CR_pack.vhd`.
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Certain other modes (A16, unaligned/byte/halfword accesses) are
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implemented in the VHDL but have not been fully tested.
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\---
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implemented in the VHDL but have not been fully
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tested.
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### Q: I use the SVEC. How can I change the base address by writing appropriate values in some registers (ADER, ADEM, and possibly others)?
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Probably the example in the documentation of the
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[VME64xCore](https://www.ohwr.org/project/vme64x-core/commits/master/documentation/user_guides/vme64x_user_manual.pdf)
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of the SVEC is the most helpful in this, as it contains worked
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examples.
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In addition, the code of [svec\_setup\_csr() in the svec device
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driver](https://www.ohwr.org/project/svec-sw/tree/master/) can also be
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very helpful in understanding how you can do the configuration by
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writing to the Address Relocation Registers.
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-----
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Davide Pedretti, Erik van der Bij, Tomasz Wlostowski - 17 March 2014
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Davide Pedretti, Erik van der Bij, Tomasz Wlostowski - 10 May 2017
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