| ... | ... | @@ -44,14 +44,12 @@ manual](https://www.ohwr.org/project/vme64x-core/commits/master/trunk/documentat |
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## Documents
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- [VME64
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ANSI/VITA 1 1994](https://www.ohwr.org/1477)
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- [VME64 Extensions
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ANSI/VITA 1.1 1997](https://www.ohwr.org/1478)
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- [Wishbone System-on-chip (SoC) Interconnection Architecture for
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Portable IP Cores, Revision
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B4](https://www.ohwr.org/1479)
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- [ANSI/VITA 1.5-2003 2eSST](https://www.ohwr.org/1480)
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- VME64 ANSI/VITA 1 1994
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- VME64 Extensions ANSI/VITA 1.1 1997
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- ANSI/VITA 1.5-2003 2eSST
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## Contacts
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| ... | ... | @@ -99,14 +97,13 @@ manual](https://www.ohwr.org/project/vme64x-core/commits/master/trunk/documentat |
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</tr>
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<tr class="odd">
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<td>30-07-2012</td>
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<td>SINGLE, BLT (D32), MBLT (D64) transfers in A16, A24, A32 and A64 address modes working on VFC V2 and SVEC V0. A ROACK type IRQ Controller is provided.</td>
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<td>SINGLE, BLT (D32), MBLT (D64) transfers in A16, A24, A32 and A64 address modes working<br />
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on VFC V2 and SVEC V0. A ROACK type IRQ Controller is provided.</td>
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</tr>
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</tbody>
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</table>
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-----
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Davide Pedretti 10 August 2012
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-----
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Davide Pedretti - 10 August 2012
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