| ... | ... | @@ -17,30 +17,33 @@ transfers. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
-----
|
|
|
|
|
|
|
|
## Main features
|
|
|
|
|
|
|
|
\* VME64x slave
|
|
|
|
o CR/CSR space
|
|
|
|
o ROACK type IRQ controller with one interrupt input and a programmable
|
|
|
|
interrupt level and Status/ID register
|
|
|
|
o Supported VME access modes
|
|
|
|
\+ SINGLE, BLT (D32), MBLT (D64)
|
|
|
|
\+ A24, A32 and A64 address modes and D08 (OE), D16, D32, D64 data
|
|
|
|
transfers
|
|
|
|
- VME64x slave
|
|
|
|
- CR/CSR space
|
|
|
|
- ROACK type IRQ controller with one interrupt input and a
|
|
|
|
programmable interrupt level and Status/ID register
|
|
|
|
- Supported VME access modes
|
|
|
|
- SINGLE, BLT (D32), MBLT (D64)
|
|
|
|
- A24, A32 and A64 address modes and D08 (OE), D16, D32, D64
|
|
|
|
data transfers
|
|
|
|
- WishBone master (user side)
|
|
|
|
- Pipelined WB master for SINGLE transfers
|
|
|
|
|
|
|
|
\* WishBone master (user side)
|
|
|
|
o Pipelined WB master for SINGLE transfers
|
|
|
|
For more details about the project see the [VME64x user
|
|
|
|
manual](https://www.ohwr.org/project/vme64x-core/commits/master/trunk/documentation/user_guides/vme64x_user_manual.pdf).
|
|
|
|
|
|
|
|
For more details about the project see [vme64x user
|
|
|
|
manual](https://www.ohwr.org/project/vme64x-core/commits/master/trunk/documentation/user_guides/vme64x_user_manual.pdf)
|
|
|
|
-----
|
|
|
|
|
|
|
|
## Project information
|
|
|
|
|
|
|
|
- [vme64x user
|
|
|
|
- [VME64x user
|
|
|
|
manual](https://www.ohwr.org/project/vme64x-core/blob/master/documentation/user_guides/vme64x_user_manual.pdf)
|
|
|
|
- [VME access
|
|
|
|
modes](https://www.ohwr.org/project/vme64x-core/blob/master/documentation/user_guides/VME_access_modes.pdf)
|
|
|
|
- [guidelines to use the vme64x
|
|
|
|
- [Guidelines to use the vme64x
|
|
|
|
core](https://www.ohwr.org/project/vme64x-core/blob/master/documentation/user_guides/Python_test.pdf)
|
|
|
|
- [*Design, implementation and test of a VME to Wishbone
|
|
|
|
interface*](https://www.ohwr.org/project/vme64x-core/wikis/Documents/Design-implementation-and-test-of-a-VME-to-WB-interface), Thesis of Davide
|
| ... | ... | @@ -48,6 +51,8 @@ manual](https://www.ohwr.org/project/vme64x-core/commits/master/trunk/documentat |
|
|
|
- [Users](Users)
|
|
|
|
- [Frequently Asked Questions](FAQ)
|
|
|
|
|
|
|
|
-----
|
|
|
|
|
|
|
|
## Documents
|
|
|
|
|
|
|
|
- [Wishbone System-on-chip (SoC) Interconnection Architecture for
|
| ... | ... | @@ -57,6 +62,8 @@ manual](https://www.ohwr.org/project/vme64x-core/commits/master/trunk/documentat |
|
|
|
- VME64 Extensions ANSI/VITA 1.1 1997
|
|
|
|
- ANSI/VITA 1.5-2003 2eSST
|
|
|
|
|
|
|
|
-----
|
|
|
|
|
|
|
|
## Contacts
|
|
|
|
|
|
|
|
### General question about project
|
| ... | ... | @@ -118,10 +125,18 @@ on VFC V2 and SVEC V0. A ROACK type IRQ Controller is provided.</td> |
|
|
|
<td>29-05-2013</td>
|
|
|
|
<td>Core re-used as basis for design at GSI.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td>29-11-2013</td>
|
|
|
|
<td>Bug <a href="https://www.ohwr.org/project/vme64x-core/issues/16">multiple cards DTACKing on same CSR address</a> found.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td>11-12-2013</td>
|
|
|
|
<td>Decided to start in 2014 a new project to rewrite/cleanup the core to make it better maintainable.</td>
|
|
|
|
</tr>
|
|
|
|
</tbody>
|
|
|
|
</table>
|
|
|
|
|
|
|
|
-----
|
|
|
|
|
|
|
|
Davide Pedretti, Erik van der Bij - 29 May 2013
|
|
|
|
Davide Pedretti, Erik van der Bij - 11 December 2013
|
|
|
|
|
