| ... | ... | @@ -5,12 +5,11 @@ |
|
|
|
The VME64x core implements a VME64 slave on one side and a WishBone
|
|
|
|
master on the other without FIFOs in-between.
|
|
|
|
|
|
|
|
The core supports SINGLE, BLT (D32), MBLT (D64) transfers in A24 and A32
|
|
|
|
The core supports SINGLE, BLT (D32), MBLT (D64) and 2eSST transfers in A24 and A32
|
|
|
|
address modes and D08 (OE), D16, D32 data transfers. The core can be
|
|
|
|
configured via implemented CR/CSR configuration space. A ROACK type IRQ
|
|
|
|
controller with one interrupt input and a programmable interrupt level
|
|
|
|
and Status/ID register is
|
|
|
|
provided.
|
|
|
|
and Status/ID register is provided.
|
|
|
|
|
|
|
|
|
|
|
|
|
| ... | ... | @@ -23,11 +22,13 @@ provided. |
|
|
|
- ROACK type IRQ controller with one interrupt input and a
|
|
|
|
programmable interrupt level and Status/ID register
|
|
|
|
- Supported VME access modes
|
|
|
|
- SINGLE, BLT (D32), MBLT (D64)
|
|
|
|
- SINGLE, BLT (D32), MBLT (D64), 2eSST (D64)
|
|
|
|
- A24 and A32 address modes and D08 (OE), D16, D32 data
|
|
|
|
transfers
|
|
|
|
- WishBone master (user side)
|
|
|
|
- Pipelined/Non-pipelined WB master.
|
|
|
|
- Performances:
|
|
|
|
- Read > 80MB/s using 2eSST mode (See [performances](Performances))
|
|
|
|
|
|
|
|
-----
|
|
|
|
|
| ... | ... | @@ -86,6 +87,7 @@ provided. |
|
|
|
|14-12-2017|Release 2.0|
|
|
|
|
|14-11-2019|Add support for d16 only masters|
|
|
|
|
|24-04-2019|Release 2.1 with prefetching for MBLT reads|
|
|
|
|
|05-10-2019|Add performances|
|
|
|
|
|
|
|
|
---
|
|
|
|
|
| ... | ... | |
