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Home.md

@@ -9,10 +9,8 @@ The core supports SINGLE, BLT (D32), MBLT (D64) transfers in A24 and A32
 address modes and D08 (OE), D16, D32 data transfers. The core can be
 configured via implemented CR/CSR configuration space. A ROACK type IRQ
 controller with one interrupt input and a programmable interrupt level
-and Status/ID register is provided.
-
-A WishBone side features a pipelined WB
-master.
+and Status/ID register is
+provided.
 
 ![](/uploads/c9c5d9563f3db625faa7bc2d4ab10051/VME64x_BlockDiagram2.png)
 
@@ -35,15 +33,7 @@ master.
 
 ## Project information
 
-  - [VME64x user
-    manual](https://www.ohwr.org/project/vme64x-core/commits/master/documentation/user_guides/vme64x_user_manual.pdf)
-  - [VME access
-    modes](https://www.ohwr.org/project/vme64x-core/blob/master/documentation/user_guides/VME_access_modes.pdf)
-  - [Guidelines to use the vme64x
-    core](https://www.ohwr.org/project/vme64x-core/blob/master/documentation/user_guides/Python_test.pdf)
-  - [*Design, implementation and test of a VME to Wishbone
-    interface*](https://www.ohwr.org/project/vme64x-core/wikis/Documents/Design-implementation-and-test-of-a-VME-to-WB-interface), Thesis of Davide
-    Pedretti
+  - [VME64x Core User Guide](https://www.ohwr.org/project/vme64x-core/wikis/Documents/vme64x-core-user-guide)
   - [Users](Users)
   - [Frequently Asked Questions](FAQ)