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address modes and D08 (OE), D16, D32 data transfers. The core can be
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configured via implemented CR/CSR configuration space. A ROACK type IRQ
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controller with one interrupt input and a programmable interrupt level
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and Status/ID register is provided.
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A WishBone side features a pipelined WB
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master.
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and Status/ID register is
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provided.
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| ... | ... | @@ -35,15 +33,7 @@ master. |
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## Project information
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- [VME64x user
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manual](https://www.ohwr.org/project/vme64x-core/commits/master/documentation/user_guides/vme64x_user_manual.pdf)
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- [VME access
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modes](https://www.ohwr.org/project/vme64x-core/blob/master/documentation/user_guides/VME_access_modes.pdf)
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- [Guidelines to use the vme64x
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core](https://www.ohwr.org/project/vme64x-core/blob/master/documentation/user_guides/Python_test.pdf)
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- [*Design, implementation and test of a VME to Wishbone
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interface*](https://www.ohwr.org/project/vme64x-core/wikis/Documents/Design-implementation-and-test-of-a-VME-to-WB-interface), Thesis of Davide
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Pedretti
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- [VME64x Core User Guide](https://www.ohwr.org/project/vme64x-core/wikis/Documents/vme64x-core-user-guide)
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- [Users](Users)
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- [Frequently Asked Questions](FAQ)
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| ... | ... | |
