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# Guide
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VME64x to Wishbone Core
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Project description
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The VME64x core implements a VME64 slave on one side and a WishBone
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master on the other without FIFOs in-between.
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The core supports SINGLE, BLT (D32), MBLT (D64), 2eVME and 2eSST
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transfers in A24, A32 and A64 address modes and D08 (OE), D16, D32, D64
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data transfers. The core can be configured via implemented CR/CSR
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configuration space. A ROACK type IRQ controller with one interrupt
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input and a programmable interrupt level and Status/ID register is
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provided.
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A WishBone side features a pipelined WB master for SINGLE transfers.
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