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VME SBC A25 PCIe to VME bridge
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VME SBC A25 PCIe to VME bridge
Commits
27511fd2
Commit
27511fd2
authored
Dec 21, 2023
by
Tristan Gingold
Committed by
Tristan Gingold
Feb 05, 2024
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generic_dcfifo_mixedw: use fifo from general core
parent
91bfd3f8
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generic_dcfifo_mixedw.vhd
hdl/16z091-01_src/Source/generic_dcfifo_mixedw.vhd
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hdl/16z091-01_src/Source/generic_dcfifo_mixedw.vhd
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27511fd2
...
...
@@ -19,9 +19,6 @@
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
library
altera_mf
;
use
altera_mf
.
altera_mf_components
.
all
;
entity
generic_dcfifo_mixedw
is
generic
(
g_device_family
:
string
:
=
"Cyclone IV GX"
;
...
...
@@ -45,37 +42,28 @@ entity generic_dcfifo_mixedw is
end
generic_dcfifo_mixedw
;
architecture
syn
of
generic_dcfifo_mixedw
is
signal
rst_n_a
:
std_logic
;
begin
dcfifo_mixed_widths_component
:
dcfifo_mixed_widths
generic
map
(
intended_device_family
=>
g_device_family
,
lpm_numwords
=>
g_fifo_depth
,
-- value assigned must comply with this equation
-- 2^(LPM_WIDTHU -1) < LPM_NUMWORDS <= 2^(LPM_WIDTHU)
lpm_showahead
=>
g_showahead
,
-- off: normal mode, on: show ahead mode
lpm_type
=>
"dcfifo_mixed_widths"
,
-- DON'T CHANGE / FIFO type
lpm_width
=>
g_data_width
,
-- width for _data_ port
lpm_widthu
=>
g_data_widthu
,
-- size of write usedw
lpm_width_r
=>
g_q_width
,
-- width for _q_ port
lpm_widthu_r
=>
g_q_widthu
,
-- size of read usedw
overflow_checking
=>
"ON"
,
-- DON'T CHANGE / protection circuit for overflow checking
rdsync_delaypipe
=>
4
,
-- nbr of read synchronization stages, internally reduced by 2 => 2 stages
read_aclr_synch
=>
"OFF"
,
underflow_checking
=>
"ON"
,
-- DON'T CHANGE / protection circuit for underflow checking
use_eab
=>
"ON"
,
-- off: FIFO implemented in logic, on: FIFO implemented using RAM blocks
write_aclr_synch
=>
"OFF"
,
wrsync_delaypipe
=>
4
-- nbr of write synchronization stages, internally reduced by 2 => 2 stages
)
port
map
(
aclr
=>
aclr
,
data
=>
data
,
rdclk
=>
rdclk
,
rdreq
=>
rdreq
,
wrclk
=>
wrclk
,
wrreq
=>
wrreq
,
q
=>
q
,
rdempty
=>
rdempty
,
wrfull
=>
wrfull
,
wrusedw
=>
wrusedw
);
rst_n_a
<=
not
aclr
;
inst_fifo
:
entity
work
.
generic_async_fifo_mixedw
generic
map
(
g_wr_width
=>
g_data_width
,
g_rd_width
=>
g_q_width
,
g_size
=>
g_fifo_depth
,
g_show_ahead
=>
g_showahead
=
"ON"
,
g_memory_implementation_hint
=>
open
)
port
map
(
rst_n_a_i
=>
rst_n_a
,
clk_wr_i
=>
wrclk
,
d_i
=>
data
,
we_i
=>
wrreq
,
wr_full_o
=>
wrfull
,
wr_count_o
=>
wrusedw
,
clk_rd_i
=>
rdclk
,
q_o
=>
q
,
rd_i
=>
rdreq
,
rd_empty_o
=>
rdempty
,
rd_count_o
=>
open
);
end
syn
;
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