... | ... | @@ -30,20 +30,10 @@ currently implemented. |
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## Supported FPGA platforms
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Manufacturer </b></td>
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<td><b> Family </b></td>
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<td><b> Hardware board </b></td>
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</tr>
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<tr class="even">
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<td>Intel</td>
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<td>Cyclone IV</td>
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<td>MEN A25 VME Single Board Computer</td>
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</tr>
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</tbody>
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</table>
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|**Manufacturer**|**Family**|**Hardware board**|
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|----|----|----|
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|Intel|Cyclone IV|MEN A25 VME Single Board Computer|
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# HDL architecture
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... | ... | @@ -78,65 +68,19 @@ Registers. These memory windows are then mapped to the wishbone |
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addresses and therefore allow accessing the WB Slave devices as well as
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generating different VME accesses (see table below).
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<table>
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<tbody>
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<tr class="odd">
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<td><b> BAR no. </b></td>
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<td><b> name </b></td>
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<td><b> offset </b></td>
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</tr>
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<tr class="even">
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<td>BAR0</td>
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<td>Version ROM</td>
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<td>0</td>
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</tr>
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<tr class="odd">
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<td>BAR0</td>
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<td>Flash</td>
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<td>200</td>
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</tr>
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<tr class="even">
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<td>BAR0</td>
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<td>VMEbus - registers</td>
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<td>10000</td>
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</tr>
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<tr class="odd">
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<td>BAR0</td>
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<td>VMEbus - A16D16 access</td>
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<td>20000</td>
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</tr>
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<tr class="even">
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<td>BAR0</td>
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<td>VMEbus - A16D32 access</td>
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<td>30000</td>
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</tr>
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<tr class="odd">
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<td>BAR1</td>
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<td>SRAM</td>
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<td>0</td>
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</tr>
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<tr class="even">
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<td>BAR2</td>
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<td>VMEbus - A24D16 access</td>
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<td>0</td>
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</tr>
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<tr class="odd">
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<td>BAR2</td>
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<td>VMEbus - A24D32 access</td>
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<td>1000000</td>
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</tr>
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<tr class="even">
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<td>BAR3</td>
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<td>VMEbus - A32 access</td>
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<td>0</td>
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</tr>
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<tr class="odd">
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<td>BAR4</td>
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<td>VMEbus - CR/CSR access</td>
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<td>0</td>
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</tr>
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</tbody>
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</table>
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|**BAR no.**|**name**|**offset**|
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|----|----|----|
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|BAR0|Version ROM|0|
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|BAR0|Flash|200|
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|BAR0|VMEbus - registers|10000|
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|BAR0|VMEbus - A16D16 access|20000|
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|BAR0|VMEbus - A16D32 access|30000|
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|BAR1|SRAM|0|
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|BAR2|VMEbus - A24D16 access|0|
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|BAR2|VMEbus - A24D32 access|1000000|
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|BAR3|VMEbus - A32 access|0|
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|BAR4|VMEbus - CR/CSR access|0|
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The ***VMEbus*** module can act as both a VME Master and a VME Slave. It
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provides several Wishbone address spaces for various types of access
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... | ... | @@ -174,4 +118,4 @@ SRAM modules. |
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### Files
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* [pcie-vme-hdl.png](/uploads/de3a50030fa9acb647827501af06eebb/pcie-vme-hdl.png) |
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\ No newline at end of file |
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* [pcie-vme-hdl.png](/uploads/de3a50030fa9acb647827501af06eebb/pcie-vme-hdl.png) |