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# PCI-Express to VME bridge
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# HDL architecture
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This wiki page describes the PCI-Express to VME bridge HDL module. It
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was originally implemented by [MEN Mikro Elektronik
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GmbH](https://www.men.de/) and later open-sourced in the context of the
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CERN's VME Single Board Computers supply contract.
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The PCIe-to-VME bridge translates the read and write operations in the
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PCIe address space to read and write transactions on the VME bus. It
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acts as a PCIe Endpoint on one side and VME bus Master on the other. The
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bridge can generate VME single cycles and block transfers. The following
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access types are currently supported:
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- VME single cycles: A16, A24, A32 with any of the D8, D16, D32 data
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widths
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- VME block transfers: A16, A24, A32 with any of the D8, D16, D32 plus
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the A32D64 multiplexed block transfer (MBLT)
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The VME block transfers are executed by a built-in Direct Memory Access
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(DMA) engine, where the blocks of data are transferred between the
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system memory and the VME bus, bypassing the CPU. In general this is a
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faster and more efficient way of exchanging multiple data words, as the
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CPU is free to continue its normal operation until the DMA engine is
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done with a programmed task. The bridge supports also some features
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added in the VME64x extensions. It is able to use the geographical
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addressing pins and generate a special type of A24 access to read and
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write the CR/CSR configuration space of VME slaves installed in the same
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crate. However, none of the fast transfer modes (2eVME, 2eSST) is
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currently
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implemented.
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### HDL architecture
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![](/uploads/de3a50030fa9acb647827501af06eebb/pcie-vme-hdl.png)
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# Supported FPGA platforms
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The internal HDL architecture of the PCIe-to-VME bridge is presented in
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the figure above. It is built around the Wishbone (WB) bus, an
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open-source computer bus often used in FPGA designs. The bridge is split
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into several VHDL modules communicating together through the central
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*Wishbone Interconnect* block. Each of these modules has its own
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function and can either control other modules (is a Wishbone Master), be
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controlled (is a Wishbone Slave) or have both interfaces:
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- *PCIe2WB* - PCI Express x4 version 1.1 Endpoint with both WB Master
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and WB Slave interface
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- *VMEbus* - VME Master with both WB Master (for DMA transfers) and WB
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Slave (for single cycle accesses) interface
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- *Flash* - WB Slave module that interfaces the Flash chip outside the
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FPGA
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- *SRAM* - WB Slave module that interfaces the SRAM chip outside the
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FPGA
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- *Version ROM* - WB Slave module with FPGA memory blocks initialized
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at synthesis time with various information about the firmware (the
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so called chameleon table)
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The ***PCIe2WB*** module is in fact a wrapper for the Intel
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auto-generated IP core. This IP core customizes a PCI Express IP block
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hardened in the Cyclone IV FPGA chip. Currently we use it as a four-lane
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PCIe version 1.1 interface with vendor Id and device Id specified by
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MEN. It provides several memory windows assigned to 4 Base Address
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Registers. These memory windows are then mapped to the wishbone
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addresses and therefore allow accessing the WB Slave devices as well as
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generating different VME accesses (see table below).
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<table>
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<tbody>
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<tr class="odd">
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<td><b> BAR no. </b></td>
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<td><b> name </b></td>
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<td><b> offset </b></td>
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</tr>
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<tr class="even">
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<td>BAR0</td>
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<td>Version ROM</td>
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<td>0</td>
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</tr>
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<tr class="odd">
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<td>BAR0</td>
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<td>Flash</td>
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<td>200</td>
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</tr>
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<tr class="even">
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<td>BAR0</td>
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<td>VMEbus - registers</td>
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<td>10000</td>
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</tr>
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<tr class="odd">
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<td>BAR0</td>
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<td>VMEbus - A16D16 access</td>
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<td>20000</td>
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</tr>
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<tr class="even">
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<td>BAR0</td>
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<td>VMEbus - A16D32 access</td>
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<td>30000</td>
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</tr>
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<tr class="odd">
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<td>BAR1</td>
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<td>SRAM</td>
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<td>0</td>
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</tr>
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<tr class="even">
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<td>BAR2</td>
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<td>VMEbus - A24D16 access</td>
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<td>0</td>
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</tr>
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<tr class="odd">
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<td>BAR2</td>
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<td>VMEbus - A24D32 access</td>
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<td>1000000</td>
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</tr>
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<tr class="even">
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<td>BAR3</td>
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<td>VMEbus - A32 access</td>
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<td>0</td>
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</tr>
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<tr class="odd">
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<td>BAR4</td>
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<td>VMEbus - CR/CSR access</td>
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<td>0</td>
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</tr>
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</tbody>
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</table>
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The ***VMEbus*** module can act as both a VME Master and a VME Slave. It
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provides several Wishbone address spaces for various types of access
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(A16, A24, A32, CR/CSR). These WB windows are then directly mapped to
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the PCIe memory windows. The behavior of this module depends on the
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detected VME crate slot where it is installed. If slot 1 is detected,
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the bridge generates system clock and reset signals to the VME
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backplane, also a bus arbiter module is activated. The VHDL module can
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also read the VME interrupt lines of all 7 levels and is equipped with a
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DMA engine. DMA is responsible for performing block transfers and
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multiplexed block transfers between the VME bus and the system memory
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without the active control of the CPU during the transfer. The
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controller can be configured by writing a set of linked buffer
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descriptors to the SRAM area (maximum 112). Each descriptor specifies
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the complete information about the
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transfer like: the source and destination device, size of the transfer,
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source and destination address, VME modifier and data width (for VME
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transactions). Additionally one can specify if the DMA should
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automatically increment the source or destination address for each
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transferred word in the block, e.g. for transferring data words to SRAM.
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The source and destination device can be any of of VME bus, PCIe2WB or
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SRAM modules.
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### Supported FPGA platforms
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Manufacturer </b></td>
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<td><b> Family </b></td>
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<td><b> Hardware board </b></td>
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</tr>
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<tr class="even">
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<td>Intel</td>
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<td>Cyclone IV</td>
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<td>MEN A25 VME Single Board Computer</td>
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</tr>
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</tbody>
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</table>
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# Documentation
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# Contacts
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- [Grzegorz Daniluk](mailto:grzegorz.daniluk@cern.ch) - CERN
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### Files
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