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# VME FMC+ Carrier (VFC-HS)
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## Project description
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The VFC-HS is an Intel Arria V based VME64x carrier for one **FMC+** Mezzanine Card (VITA 57.4). It is has six SFP+ transceivers compatible with support for rad-hard [GBT](https://espace.cern.ch/GBT-Project/default.aspx) links, CERN Beam Synchronous Timing (BST), [White Rabbit](https://www.ohwr.org/project/white-rabbit/) and Ethernet.
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This card is an upgrade of the [VFC-HD](https://ohwr.org/project/vfc-hd/wikis/home) for fast sampling applications. It has been developed by the Beam Instrumentation (BI) group at CERN.
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[](/uploads/d982c5cfbe194f6fef7616bc7c01345c/vfc-hd.jpg)
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## Main features
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- Intel Arria V GT FPGA (5AGTFD7K3F40I3N)
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- FMC+ slot
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- Fully populated LA, HA & HB banks
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- 16 gigabit lanes connected to FPGA transceivers
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- Programmable Vadj
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- 6 SFP+ running up to 10Gbps
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- 4 "application" SFPs for GBT connections
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- 2 "system" SFPs for BST/White Rabbit & Ethernet
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- 40 single ended (or 20 LVDS) connections to VME P2 available for rear transition modules
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- 30 single ended connections to VME64x P0 to support clock & trigger distribution in (custom) BI LHC VME crates
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- Flexible clocking resources
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- Si570 10-280MHz programmable oscillator
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- ADN2814 CDR for BST reception
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- 125MHz & 20MHz VCXOs for White Rabbit support
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- Si5338 clock synthesizer
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- DDR3 memory on board
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- Front panel connectivity:
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- 6 SFP+ cages
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- 4 LEMO-00 general purpose I/O
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- 8 user LEDs
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- 12 layer PCB
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-----
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## Project information
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- Official design data [EDMS EDA-03836](https://edms.cern.ch/nav/EDA-03836)
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- LHC equipment name: **HC-BOEVB**
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- Schematic diagram: [EDA-03836-V1-0_sch.pdf](https://edms.cern.ch/file/1966376/1/EDA-03836-V1-0_sch.pdf)
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- Bill of material: [EEDA-03836-V1-0_pcb-mat.pdf](https://edms.cern.ch/ui/file/1966380/1/EDA-03836-V1-0_pcb-mat.pdf)
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### Users
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- **CERN Beam Instrumentation Group**
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### Contact
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- [Andrea Boccardi](@boccardi) - CERN
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-----
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## Status
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|**Date**|**Event**|
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|----|----|
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\ No newline at end of file |
