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urv-core
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Cycle Analytics
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Bug: register x0 should be hardwired to zero
#8
· opened
Feb 12, 2024
by
Shareef Jalloq
5
updated
Feb 16, 2024
Use Verible for Verilog formatting
#5
· opened
Feb 05, 2024
by
Shareef Jalloq
3
updated
Feb 14, 2024
Linting issues
#4
· opened
Feb 05, 2024
by
Shareef Jalloq
1
updated
Feb 12, 2024