Merge branch 'mlevicnik-master-patch-40238' into 'master'

Mlevicnik master patch 40238 See merge request !8

Merge branch 'mlevicnik-master-patch-40238' into 'master'
Mlevicnik master patch 40238 See merge request !8
03ccba19 · A. Hahn · c2f64228 · d481a65b · c2f64228 · c2f64228
Commit 03ccba19 authored Oct 30, 2023 by A. Hahn
11 changed files
--- a/PEXP_REVA/.gitkeep
+++ b/PEXP_REVA/.gitkeep
--- a/PEXP_REVB/.gitkeep
+++ b/PEXP_REVB/.gitkeep
--- a/PEXP_REVB/PCB/FTRN_PCIE_REVB_PCB.pdf
+++ b/PEXP_REVB/PCB/FTRN_PCIE_REVB_PCB.pdf
--- a/PEXP_REVB/PCB/FTRN_PCIe_REVB.brd
+++ b/PEXP_REVB/PCB/FTRN_PCIe_REVB.brd
--- a/PEXP_REVB/SCH/FTRN_PCIE_REVB.opj
+++ b/PEXP_REVB/SCH/FTRN_PCIE_REVB.opj
+(ExpressProject ""
+  (ProjectVersion "19981106")
+  (SoftwareVersion "17.4-2019 S029 (4024845)  [4/15/2022]-[05/12/20]")
+  (ProjectType "PCB")
+  (Folder "Design Resources"
+    (Folder "Library")
+    ("Allegro Netlist Directory" "allegro")
+    (File ".\ftrn_pcie_revb.dsn"
+      (Type "Schematic Design"))
+    (BuildFileAddedOrDeleted "x")
+    (CompileFileAddedOrDeleted "x")
+    (DOCKED "TRUE")
+    (DOCKING_POSITION "59420")
+    (NoModify)
+    (BOM_Scope "0")
+    (BOM_Mode "0")
+    (BOM_Report_File
+       "D:\SVNWORKSPACE\GSI\TIMING\TRUNK\CIRCUIT_BOARD\PCIE_AKA_PMCREVP\REVB\SCH\FTRN_PCIE_REVB.BOM")
+    (BOM_Merge_Include "FALSE")
+    (BOM_Property_Combine_7.0 "{Item}\t{Quantity}\t{Reference}\t{Value}")
+    (BOM_Header "Item\tQuantity\tReference\tPart")
+    (BOM_Include_File
+       "D:\SVNWORKSPACE\GSI\TIMING\TRUNK\CIRCUIT_BOARD\PCIE_AKA_PMCREVP\REVB\SCH\FTRN_PCIE_REVB.INC")
+    (BOM_Include_File_Combine_7.0 "{Item}\t{Quantity}\t{Reference}\t{Value}")
+    (BOM_One_Part_Per_Line "FALSE")
+    (Open_BOM_in_Excel "FALSE")
+    (BOM_View_Output "FALSE"))
+  (Folder "Layout")
+  (Folder "Outputs"
+    (File ".\ftrn_pcie_revb.bom"
+      (Type "Report")))
+  (Folder "Referenced Projects")
+  (Folder "PSpice Resources"
+    (Folder "Simulation Profiles")
+    (Folder "Model Libraries"
+      (Sort User))
+    (Folder "Stimulus Files"
+      (Sort User))
+    (Folder "Include Files"
+      (Sort User)))
+  (Folder "Logs")
+  (PartMRUSelector)
+  (GlobalState
+    (FileView
+      (Path "Design Resources")
+      (Path "Design Resources" ".\ftrn_pcie_revb.dsn")
+      (Path "Design Resources" ".\ftrn_pcie_revb.dsn" "SCHEMATIC1")
+      (Path "Outputs")
+      (Select "Design Resources" ".\ftrn_pcie_revb.dsn" "SCHEMATIC1"
+         "p01_Title_page"))
+    (HierarchyView)
+    (Doc
+      (Type "COrCapturePMDoc")
+      (Frame
+        (Placement "44 0 1 -1 -1 -1 -1 0 200 0 837"))
+      (Tab 0))
+    (Doc
+      (Type "COrSchematicDoc")
+      (Frame
+        (Placement "44 0 1 -1 -1 -1 -1 5 1378 24 855")
+        (Scroll "0 0")
+        (Zoom "100")
+        (Occurrence "/"))
+      (Path
+         "D:\SVNWORKSPACE\GSI\TIMING\TRUNK\CIRCUIT_BOARD\PCIE_AKA_PMCREVP\REVB\SCH\FTRN_PCIE_REVB.DSN")
+      (Schematic "SCHEMATIC1")
+      (Page "p01_Title_page")))
+  (MPSSessionName "mlevicnik"))
--- a/PEXP_REVB/SCH/FTRN_PCIE_REVB_SCH.pdf
+++ b/PEXP_REVB/SCH/FTRN_PCIE_REVB_SCH.pdf
--- a/PEXP_REVB/SCH/FTRN_PCIe_REVB.DSN
+++ b/PEXP_REVB/SCH/FTRN_PCIe_REVB.DSN
--- a/PEXP_REVB/gerber/FTRN_PCIe_REVB_Assembly_7620.pdf
+++ b/PEXP_REVB/gerber/FTRN_PCIe_REVB_Assembly_7620.pdf
--- a/PEXP_REVB/gerber/FTRN_PCIe_REVB_BOM_P&P_7620.xlsx
+++ b/PEXP_REVB/gerber/FTRN_PCIe_REVB_BOM_P&P_7620.xlsx
--- a/PEXP_REVB/gerber/FTRN_PCIe_REVB_Gerber_7620.zip
+++ b/PEXP_REVB/gerber/FTRN_PCIe_REVB_Gerber_7620.zip
--- a/PEXP_REVB/gerber/FTRN_PCIe_REVB_TechnicalDocument.pdf
+++ b/PEXP_REVB/gerber/FTRN_PCIe_REVB_TechnicalDocument.pdf