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Commit ed071f07 authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : clock padding block was modified for the new requirements 

 On branch development

	modified:   fpga/sources/src_clkpadding/clkpadding_top.vhdl
	modified:   fpga/sources/src_freqDIV/freqDIV_monitoring.vhdl
	modified:   fpga/sources/testbench/clkpadding_tb.vhdl
parent bb09df8a
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Showing with 46 additions and 19 deletions
fpga/sources/src_clkpadding/clkpadding_top.vhdl
View file @ ed071f07
......@@ -6,11 +6,13 @@
-- clock is missing on the input.
-- It is used by Cristal laser synchro system to avoid gaps in the
-- 1 kHz clock when changing delays
-- The laser frequency is :
-- Fl = Frf / 2 / 0x2AF60 = 1000.7397555 Hz (999.261 s)
--------------------------------------------------------------------------------
-- File : clkpadding_top.vhdl
-- Revision : x.x.x
-- Created : July 19, 2014
-- Updated : Septembre 19, 2014
-- Updated : December 08, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -65,17 +67,21 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
constant c_gapDetect : unsigned (11 downto 0) := X"34F";
constant c_paddingPeriod : unsigned (11 downto 0) := X"34D"; -- 1000.73839 Hz
constant c_pulseHigh : unsigned (07 downto 0) := X"A9"; -- 200 s
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_cnt1 : unsigned (8 downto 0); -- counter
signal s_cnt2 : unsigned (8 downto 0); -- counter
signal s_cnt1 : unsigned (11 downto 0); -- counter
signal s_cnt2 : unsigned (11 downto 0); -- counter
signal s_start : std_logic;
signal s_underProgress : std_logic;
signal s_clkPadding : std_logic;
signal s_reset : std_logic;
signal s_extCLKup : std_logic;
signal s_led : std_logic;
signal s_ledHold : std_logic;
......@@ -85,13 +91,13 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
begin
-- Detection of a gap in the input clock
process (s_reset, p_clkPADDING_clk_sr)
process (p_clkPADDING_reset, s_reset, p_clkPADDING_clk_sr)
begin
if (s_reset = '1') then
if ((p_clkPADDING_reset = '1') or (s_reset = '1')) then
s_cnt1 <= (OTHERS => '0');
s_start <= '0';
elsif (rising_edge(p_clkPADDING_clk_sr)) then
if (s_cnt1 = X"1A9") then
if (s_cnt1 = c_gapDetect) then
s_start <= '1';
s_cnt1 <= s_cnt1;
else
......@@ -106,26 +112,48 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
begin
if (p_clkPADDING_reset = '1') then
s_cnt2 <= (OTHERS => '0');
s_underProgress <= '0';
s_clkPadding <= p_clkPADDING_clk_mon;
elsif (rising_edge(p_clkPADDING_clk_sr)) then
if ((s_start = '1') or (s_underProgress = '1')) then
if (s_start = '1') then
s_cnt2 <= s_cnt2 + 1;
if (s_cnt2 < X"1A2") then
s_underProgress <= '1';
s_clkPadding <= '1';
if (s_cnt2 < c_pulseHigh) then
s_clkPadding <= '1';
elsif (s_cnt2 < c_paddingPeriod) then
s_clkPadding <= '0';
else
s_cnt2 <= (OTHERS => '0');
s_underProgress <= '0';
s_cnt2 <= (OTHERS => '0');
s_clkPadding <= '0';
end if;
else
s_cnt2 <= (OTHERS => '0');
s_underProgress <= '0';
s_clkPadding <= p_clkPADDING_clk_mon;
end if;
end if;
end process;
-- Reset the padding if the external clock is on
process (p_clkPADDING_reset, s_reset, p_clkPADDING_clk_mon)
begin
if ((p_clkPADDING_reset = '1') or (s_reset = '1')) then
s_extCLKup <= '0';
elsif (rising_edge(p_clkPADDING_clk_mon)) then
s_extCLKup <= '1';
end if;
end process;
process (p_clkPADDING_reset, p_clkPADDING_clk_sr)
begin
if (p_clkPADDING_reset = '1') then
s_reset <= '0';
elsif (rising_edge(p_clkPADDING_clk_sr)) then
if (s_extCLKup = '1') then
s_reset <= '1';
else
s_reset <= '0';
end if;
end if;
end process;
-- Trigger red LED
process (p_clkPADDING_reset, s_start, p_clkPADDING_clk500mHz)
begin
......@@ -140,7 +168,6 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
------------------------------------------------------------------------------
------------------------------------------------------------------------------
s_reset <= p_clkPADDING_reset or s_clkPadding;
p_clkPADDING_outTTL(0) <= '0'; -- not used ; is configured as input
p_clkPADDING_outTTL(1) <= '0'; -- not used ; is configured as input
......
fpga/sources/src_freqDIV/freqDIV_monitoring.vhdl
View file @ ed071f07
......@@ -61,7 +61,7 @@ architecture rtl_freqDIV_monitoring of freqDIV_monitoring is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
constant s_cntmax : unsigned (31 downto 0) := X"FFFFFFFF";
constant c_cntmax : unsigned (31 downto 0) := X"FFFFFFFF";
------------------------------------------------------------------------------
-- signal
......@@ -104,7 +104,7 @@ architecture rtl_freqDIV_monitoring of freqDIV_monitoring is
if ((s_stop = '1') or (p_reset = '1')) then
s_cnt <= (OTHERS => '0');
elsif (falling_edge(p_clk1kHz)) then
if (s_cnt < s_cntmax) then
if (s_cnt < c_cntmax) then
s_cnt <= s_cnt + 1;
else
s_cnt <= s_cnt; -- keep the max value in case of overflow
......
fpga/sources/testbench/clkpadding_tb.vhdl
View file @ ed071f07
......@@ -52,8 +52,8 @@ architecture simu_clkPADDING_tb of clkPADDING_tb is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
constant period_846kHz : TIME := 1181.14 ns;
constant period_1kHz : TIME := 999244.75 ns;
constant period_846kHz : TIME := 1181.16 ns;
constant period_1kHz : TIME := 999260.79 ns;
constant delta : TIME := 171736 ns;
constant shortDelta : TIME := 4600 ns;
......
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