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TimEX3
Commit e2908ab6 authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : MIK optimization and bug correction 

 On branch development

	modified:   fpga/TimEX3/top.ucf
	modified:   fpga/sources/clk_sources.vhdl
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_MIK/MIK_detection.vhdl
	modified:   fpga/sources/src_MIK/MIK_duplication.vhdl
	modified:   fpga/sources/src_MIK/MIK_top.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_registerMux.vhdl
	modified:   fpga/sources/top.vhdl
parent 102cfadf
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Showing with 40 additions and 35 deletions
fpga/TimEX3/top.ucf
View file @ e2908ab6
......@@ -312,7 +312,7 @@ NET "pin_WRn" SLEW = FAST;
NET "pin_CLK60MHz" CLOCK_DEDICATED_ROUTE = TRUE;
NET "s_clk60MHz" CLOCK_DEDICATED_ROUTE = TRUE;
PIN "s_clk120MHz_BUFG.O" CLOCK_DEDICATED_ROUTE = TRUE;
PIN "s_clk240MHz_BUFG.O" CLOCK_DEDICATED_ROUTE = TRUE;
NET "pin_inTTL[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "pin_CLK60MHz" TNM_NET = "pin_CLK60MHz";
......
fpga/sources/clk_sources.vhdl
View file @ e2908ab6
......@@ -7,7 +7,7 @@
-- File : clk_sources.vhd
-- Revision : x.x.x
-- Created : October 30, 2012
-- Updated : April 29, 2015
-- Updated : April 30, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -48,7 +48,7 @@ use UNISIM.vcomponents.all;
entity clk_sources is
port (
p_clk60MHz : in std_logic; -- clock 60 MHz
p_clk120MHz : out std_logic; -- clock 120 MHz
p_clk240MHz : out std_logic; -- clock 120 MHz
p_reset : in std_logic; -- reset input
p_clk1kHz : out std_logic; -- clock 0.1 Hz
p_clk500mHz : out std_logic -- clock 0.5 Hz
......@@ -74,7 +74,6 @@ architecture rtl_clk_sources of clk_sources is
signal s_cnt : unsigned (8 downto 0); -- counter
signal s_clk1kHz : std_logic;
signal s_clk500mHz : std_logic;
signal s_clk0 : std_logic;
signal GND_BIT : std_logic;
......@@ -82,10 +81,10 @@ architecture rtl_clk_sources of clk_sources is
-- Attributes
------------------------------------------------------------------------------
attribute PERIOD : string;
attribute PERIOD of p_clk120MHz : signal is "8 ns";
attribute PERIOD of p_clk240MHz : signal is "4 ns";
attribute BUFFER_TYPE : string;
attribute BUFFER_TYPE of p_clk120MHz : signal is "BUFG";
attribute BUFFER_TYPE of p_clk240MHz : signal is "BUFG";
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
......@@ -155,7 +154,7 @@ architecture rtl_clk_sources of clk_sources is
CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
CLKIN_PERIOD => 16.7, -- Input clock period specified in nS
CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X)
CLK_FEEDBACK => "NONE", -- Feedback source (NONE, 1X, 2X)
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
......@@ -166,19 +165,19 @@ architecture rtl_clk_sources of clk_sources is
STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
port map (
CLK0 => s_clk0, -- 1-bit output: 0 degree clock output
CLK0 => open, -- 1-bit output: 0 degree clock output
CLK180 => open, -- 1-bit output: 180 degree clock output
CLK270 => open, -- 1-bit output: 270 degree clock output
CLK2X => p_clk120MHz, -- 1-bit output: 2X clock frequency clock output
CLK2X => open, -- 1-bit output: 2X clock frequency clock output
CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
CLK90 => open, -- 1-bit output: 90 degree clock output
CLKDV => open, -- 1-bit output: Divided clock output
CLKFX => open, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
CLKFX => p_clk240MHz, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
LOCKED => open, -- 1-bit output: DCM_SP Lock Output
PSDONE => open, -- 1-bit output: Phase shift done output
STATUS => open, -- 8-bit output: DCM_SP status output
CLKFB => s_clk0, -- 1-bit input: Clock feedback input
CLKFB => GND_BIT, -- 1-bit input: Clock feedback input
CLKIN => p_clk60MHz, -- 1-bit input: Clock input
DSSEN => GND_BIT, -- 1-bit input: Unsupported, specify to GND.
PSCLK => GND_BIT, -- 1-bit input: Phase shift clock input
......
fpga/sources/registers_init.vhdl
View file @ e2908ab6
......@@ -77,7 +77,7 @@ package registers_init is
X"00000000", X"000493E0",
-- *** MIK ***
-- time between 2 pulses (read only), maximum delay before a missing synchro is signaled, pulse width
X"00000000", X"000493E0", X"000001E0");
X"00000000", X"000493E0", X"000003C0");
-- Read registers
constant c_board_id : std_logic_vector (31 downto 0) := X"4AC0FA5C"; -- board ID for TimEX3
......
fpga/sources/src_MIK/MIK_detection.vhdl
View file @ e2908ab6
......@@ -49,7 +49,7 @@ entity MIK_detection is
port (
p_reset : in std_logic; -- global reset
p_clk60MHz : in std_logic; -- 60 MHz clock
p_clk120MHz : in std_logic; -- 120 MHz clock
p_clk240MHz : in std_logic; -- 120 MHz clock
p_in : in std_logic; -- input
p_pulseWidth : in std_logic_vector (31 downto 0); -- pulse width register
p_csw : in std_logic; -- register chip select
......@@ -73,8 +73,10 @@ architecture rtl_MIK_detection of MIK_detection is
signal s_resync : std_logic_vector (2 downto 0);
-- s_risingEdge : std_logic;
-- s_fallingEdge : std_logic;
signal s_cntPulseWidth : unsigned (31 downto 0);
signal s_cntPulseWidthMax : unsigned (31 downto 0);
-- signal s_cntPulseWidth : unsigned (31 downto 0);
-- signal s_cntPulseWidthMax : unsigned (31 downto 0);
signal s_cntPulseWidth : unsigned (9 downto 0);
signal s_cntPulseWidthMax : unsigned (9 downto 0);
signal s_start : std_logic;
signal s_end : std_logic;
signal s_rstCNT : std_logic;
......@@ -85,11 +87,11 @@ architecture rtl_MIK_detection of MIK_detection is
begin
-- Resync input
process (p_reset, p_clk120MHz)
process (p_reset, p_clk240MHz)
begin
if (p_reset = '1') then
s_resync <= "000";
elsif (rising_edge(p_clk120MHz)) then
elsif (rising_edge(p_clk240MHz)) then
s_resync <= s_resync (1 downto 0) & p_in;
-- s_risingEdge <= s_resync(1) and not s_resync(2);
-- s_fallingEdge <= s_resync(2) and not s_resync(1);
......@@ -109,13 +111,14 @@ architecture rtl_MIK_detection of MIK_detection is
end process;
-- Pulse generation
process (p_reset, s_rstCNT, s_start, p_clk120MHz)
process (p_reset, s_rstCNT, s_start, p_clk240MHz)
begin
if ((p_reset = '1') or (s_rstCNT = '1') or (s_start = '0')) then
s_cntPulseWidth <= X"00000001";
-- s_cntPulseWidth <= X"00000001";
s_cntPulseWidth <= "0000000000";
s_end <= '0';
p_out <= '0';
elsif (rising_edge(p_clk120MHz)) then
elsif (rising_edge(p_clk240MHz)) then
-- Counting the hold off time
if (s_cntPulseWidth >= s_cntPulseWidthMax) then
-- Start the gating windows
......@@ -134,11 +137,11 @@ architecture rtl_MIK_detection of MIK_detection is
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_cntPulseWidthMax <= unsigned (c_wRegister_init(18));
s_cntPulseWidthMax <= unsigned (c_wRegister_init(18) (9 downto 0));
s_rstCNT <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw = '1') then
s_cntPulseWidthMax <= unsigned (p_pulseWidth);
s_cntPulseWidthMax <= unsigned (p_pulseWidth (9 downto 0));
s_rstCNT <= '1';
else
s_cntPulseWidthMax <= s_cntPulseWidthMax;
......
fpga/sources/src_MIK/MIK_duplication.vhdl
View file @ e2908ab6
......@@ -69,10 +69,10 @@ architecture rtl_MIK_duplication of MIK_duplication is
------------------------------------------------------------------------------
begin
p_outTTL(4) <= not p_in;
p_outTTL(3) <= not p_in;
p_outTTL(2) <= not p_in;
p_outTTL(1) <= not p_in;
p_outTTL(4) <= p_in;
p_outTTL(3) <= p_in;
p_outTTL(2) <= p_in;
p_outTTL(1) <= p_in;
-- Unused signals
......
fpga/sources/src_MIK/MIK_top.vhdl
View file @ e2908ab6
......@@ -54,7 +54,7 @@ entity MIK_top is
p_MIK_clk1kHz : in std_logic;
p_MIK_clk500mHz : in std_logic;
p_MIK_clk60MHz : in std_logic;
p_MIK_clk120MHz : in std_logic;
p_MIK_clk240MHz : in std_logic;
p_MIK_pulseWidth : in std_logic_vector (31 downto 0);
p_MIK_missingPulseDelay : in std_logic_vector (31 downto 0);
p_MIK_csw : in std_logic_vector (1 downto 0);
......@@ -88,7 +88,7 @@ architecture rtl_MIK_top of MIK_top is
port map (
p_reset => p_MIK_reset,
p_clk60MHz => p_MIK_clk60MHz,
p_clk120MHz => p_MIK_clk120MHz,
p_clk240MHz => p_MIK_clk240MHz,
p_in => p_MIK_inTTL, -- TTL in
p_pulseWidth => p_MIK_pulseWidth,
p_csw => p_MIK_csw(0),
......
fpga/sources/src_cPCI/cPCI_registerMux.vhdl
View file @ e2908ab6
......@@ -16,7 +16,7 @@
-- File : cPCI_registerMux.vhdl
-- Revision : x.x.x
-- Created : November 17, 2013
-- Updated : April 29, 2015
-- Updated : April 30, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -176,11 +176,11 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
-- MIK pulse generator
with p_mux_SWsel select
p_mux_wRegister(16) <=
p_wRegister(0) when "000000",
p_wRegister(0) when "000111",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_mux_wRegister(17) <=
p_wRegister(1) when "000000",
p_wRegister(1) when "000111",
X"00000000" when OTHERS;
------------------------------------------------------------------------------
......@@ -408,8 +408,11 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_csr(13) <= p_mux_csr(13);
p_csr(14) <= p_mux_csr(14);
p_csr(15) <= p_mux_csr(15);
p_csr(16) <= p_mux_csr(16);
p_csr(17) <= p_mux_csr(17);
p_csr(18) <= p_mux_csr(18);
p_csr (20 downto 16) <= "00000";
p_csr (20) <= '0';
------------------------------------------------------------------------------
------------------------------------------------------------------------------
......
fpga/sources/top.vhdl
View file @ e2908ab6
......@@ -168,7 +168,7 @@ architecture rtl_top of top is
signal s_mux_csw : std_logic_vector (15 downto 0);
signal s_mux_csr : std_logic_vector (15 downto 0);
signal s_clk60MHz : std_logic; -- 60 MHz clock
signal s_clk120MHz : std_logic; -- 120 MHz clock
signal s_clk240MHz : std_logic; -- 120 MHz clock
signal s_clk1kHz : std_logic; -- 1 kHz clock
signal s_clk500mhz : std_logic; -- 0.5 Hz clock
signal s_reset : std_logic;
......@@ -268,7 +268,7 @@ architecture rtl_top of top is
clk_gen : entity work.clk_sources (rtl_clk_sources)
port map (
p_clk60MHz => s_clk60MHz, -- clock 60 MHz
p_clk120MHz => s_clk120MHz, -- clock 120 MHz
p_clk240MHz => s_clk240MHz, -- clock 120 MHz
p_reset => s_reset, -- reset in
p_clk1kHz => s_clk1kHz, -- clock 1 KHz
p_clk500mHz => s_clk500mhz -- clock 0.5 Hz
......@@ -598,7 +598,7 @@ architecture rtl_top of top is
p_MIK_clk1kHz => s_clk1kHz,
p_MIK_clk500mHz => s_clk500mhz,
p_MIK_clk60MHz => s_clk60MHz,
p_MIK_clk120MHz => s_clk120MHz,
p_MIK_clk240MHz => s_clk240MHz,
p_MIK_pulseWidth => s_MIKpulseWidth, -- pulse width
p_MIK_missingPulseDelay => s_MIKmissingPulseDelay, -- maximum delay before a missing synchro
-- pulse is signaled
......
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