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TimEX3
Commit 0258cddf authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : corrected a mistake in the clock padding function. Output should 

be a directe copy of the input when available without being clocking

 On branch development

	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_clkpadding/clkpadding_top.vhdl
	modified:   fpga/sources/testbench/clkpadding_tb.vhdl
	modified:   pcb/gerber/Transcode Report.txt
	modified:   sch/timex3_sch.pro
parent 39b18588
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Showing with 280 additions and 26 deletions
fpga/sources/registers_init.vhdl
View file @ 0258cddf
......@@ -9,7 +9,7 @@
-- File : registers_init.vhdl
-- Revision : x.x.x
-- Created : March 06, 2013
-- Updated : May 03, 2015
-- Updated : November 26, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -81,7 +81,7 @@ package registers_init is
-- Read registers
constant c_board_id : std_logic_vector (31 downto 0) := X"4AC0FA5C"; -- board ID for TimEX3
constant c_firmware_rev : std_logic_vector (31 downto 0) := X"000000C1"; -- firmware's version
constant c_firmware_rev : std_logic_vector (31 downto 0) := X"000000C2"; -- firmware's version
end package registers_init;
......
fpga/sources/src_clkpadding/clkpadding_top.vhdl
View file @ 0258cddf
......@@ -12,14 +12,14 @@
-- File : clkpadding_top.vhdl
-- Revision : x.x.x
-- Created : July 19, 2014
-- Updated : December 08, 2014
-- Updated : November 27, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
-- Copyright (C) 2012 - 2015 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -80,12 +80,16 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
signal s_start : std_logic;
signal s_underProgress : std_logic;
signal s_clkPadding : std_logic;
signal s_clk_OUT : std_logic;
signal s_reset : std_logic;
signal s_extCLKup : std_logic;
signal s_led : std_logic;
signal s_ledHold : std_logic;
------------------------------------------------------------------------------
-- attribute keep : string;
-- attribute keep of s_clkPadding : signal is "True";
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
......@@ -108,11 +112,11 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
-- Generation of a padding clock if a gap is detected
-- in the input clock
process (p_clkPADDING_reset, p_clkPADDING_clk_sr)
process (p_clkPADDING_reset, p_clkPADDING_clk_sr, p_clkPADDING_clk_mon)
begin
if (p_clkPADDING_reset = '1') then
s_cnt2 <= (OTHERS => '0');
s_clkPadding <= p_clkPADDING_clk_mon;
s_clkPadding <= '0';
elsif (rising_edge(p_clkPADDING_clk_sr)) then
if (s_start = '1') then
s_cnt2 <= s_cnt2 + 1;
......@@ -126,7 +130,7 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
end if;
else
s_cnt2 <= (OTHERS => '0');
s_clkPadding <= p_clkPADDING_clk_mon;
s_clkPadding <= '0';
end if;
end if;
end process;
......@@ -154,6 +158,12 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
end if;
end process;
-- Multiplex the output according to the input state
with s_start select
s_clk_OUT <=
s_clkPadding when '1',
p_clkPADDING_clk_mon when OTHERS;
-- Trigger red LED
process (p_clkPADDING_reset, s_start, p_clkPADDING_clk500mHz)
begin
......@@ -171,8 +181,10 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
p_clkPADDING_outTTL(0) <= '0'; -- not used ; is configured as input
p_clkPADDING_outTTL(1) <= '0'; -- not used ; is configured as input
p_clkPADDING_outTTL(2) <= s_clkPadding;
p_clkPADDING_outTTL(3) <= s_clkPadding;
-- p_clkPADDING_outTTL(2) <= s_clkPadding;
-- p_clkPADDING_outTTL(3) <= s_clkPadding;
p_clkPADDING_outTTL(2) <= s_clk_OUT;
p_clkPADDING_outTTL(3) <= s_clk_OUT;
p_clkPADDING_outTTL(4) <= p_clkPADDING_clk_mon;
p_clkPADDING_outPECL(4 downto 0) <= "00000";
......
fpga/sources/testbench/clkpadding_tb.vhdl
View file @ 0258cddf
......@@ -7,14 +7,14 @@
-- File : clkPADDING_td.vhdl
-- Revision : x.x.x
-- Created : July 19, 2014
-- Updated : Septembre 19, 2014
-- Updated : November 27, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
-- Copyright (C) 2012 - 2015 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -55,7 +55,9 @@ architecture simu_clkPADDING_tb of clkPADDING_tb is
constant period_846kHz : TIME := 1181.16 ns;
constant period_1kHz : TIME := 999260.79 ns;
constant delta : TIME := 171736 ns;
constant shortDelta : TIME := 4600 ns;
constant delta500n : TIME := 500 ns;
constant delta1u : TIME := 1000 ns;
constant delta5u : TIME := 4600 ns;
constant delta50u : TIME := 50000 ns;
------------------------------------------------------------------------------
......@@ -103,7 +105,7 @@ architecture simu_clkPADDING_tb of clkPADDING_tb is
s_clk500mHz <= '1';
wait for (period_1kHz);
end process;
process
begin
......@@ -374,7 +376,7 @@ architecture simu_clkPADDING_tb of clkPADDING_tb is
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for shortDelta;
wait for delta5u;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
......@@ -382,7 +384,7 @@ architecture simu_clkPADDING_tb of clkPADDING_tb is
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for shortDelta;
wait for delta5u;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
......@@ -390,7 +392,7 @@ architecture simu_clkPADDING_tb of clkPADDING_tb is
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for shortDelta;
wait for delta5u;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
......@@ -398,7 +400,7 @@ architecture simu_clkPADDING_tb of clkPADDING_tb is
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for shortDelta;
wait for delta5u;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
......@@ -406,7 +408,7 @@ architecture simu_clkPADDING_tb of clkPADDING_tb is
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for shortDelta;
wait for delta5u;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
......@@ -414,7 +416,7 @@ architecture simu_clkPADDING_tb of clkPADDING_tb is
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for shortDelta;
wait for delta5u;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
......@@ -533,6 +535,145 @@ architecture simu_clkPADDING_tb of clkPADDING_tb is
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
---------------------------
---------------------------
wait for (period_1kHz / 2);
s_clkTimBeL <= '1';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for delta500n;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for delta500n;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for delta500n;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for delta500n;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for delta500n;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for delta500n;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for (period_1kHz);
wait for (period_1kHz);
wait for (period_1kHz);
wait for (period_1kHz);
s_chgMark <= '0';
---------------------------
s_chgMark <= '1';
wait for delta500n;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for delta500n;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for delta1u;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for delta1u;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for delta1u;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for (period_1kHz);
wait for (period_1kHz);
wait for (period_1kHz);
wait for (period_1kHz);
s_chgMark <= '0';
---------------------------
s_chgMark <= '1';
wait for delta500n;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
---------------------------
s_chgMark <= '1';
wait for delta500n;
s_clkTimBeL <= '1';
s_chgMark <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '1';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '1';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
s_clkTimBeL <= '1';
wait for (period_1kHz / 2);
s_clkTimBeL <= '0';
wait for (period_1kHz / 2);
s_chgMark <= '0';
-- *** END ***
wait;
end process;
......
pcb/gerber/Transcode Report.txt
View file @ 0258cddf
......@@ -615,4 +615,110 @@ D49 --> D335
D50 --> D336
D52 --> D337
D53 --> D338
-----------------------------------------------------------------
---- Transcoding 'D:\jpr\projets\TimEX3\pcb\gerber\45123f1.274x' ---- Tue Jun 23 16:24:36 2015
D10 --> D272
D11 --> D273
D12 --> D274
D13 --> D275
D14 --> D276
D15 --> D277
D16 --> D278
D17 --> D279
D18 --> D280
D19 --> D281
D20 --> D282
D21 --> D283
D22 --> D284
D23 --> D285
D24 --> D286
D25 --> D287
D26 --> D288
D27 --> D289
D28 --> D290
D29 --> D291
D30 --> D292
D31 --> D293
D32 --> D294
D33 --> D295
D34 --> D296
D35 --> D297
D36 --> D298
D37 --> D299
D38 --> D300
D39 --> D301
D40 --> D302
D41 --> D303
D42 --> D304
D43 --> D305
D44 --> D306
D45 --> D307
D46 --> D308
D47 --> D309
D48 --> D310
D49 --> D311
D50 --> D312
D51 --> D313
D52 --> D314
D53 --> D315
D54 --> D316
D55 --> D317
D56 --> D318
D57 --> D319
D58 --> D320
-----------------------------------------------------------------
---- Transcoding 'D:\jpr\projets\TimEX3\pcb\gerber\45123v1.274x' ---- Tue Jun 23 16:25:27 2015
D10 --> D321
D11 --> D322
D12 --> D323
D13 --> D324
D14 --> D325
D15 --> D326
D16 --> D327
D17 --> D328
D18 --> D329
D19 --> D330
D20 --> D331
D21 --> D332
D22 --> D333
D23 --> D334
D24 --> D335
D25 --> D336
D26 --> D337
D27 --> D338
D28 --> D339
D29 --> D340
D30 --> D341
D31 --> D342
D32 --> D343
D33 --> D344
D34 --> D345
D35 --> D346
D36 --> D347
D37 --> D348
D38 --> D349
D39 --> D350
D40 --> D351
D41 --> D352
D42 --> D353
D43 --> D354
D44 --> D355
D45 --> D356
D46 --> D357
D47 --> D358
D48 --> D359
D49 --> D360
D50 --> D361
D51 --> D362
D52 --> D363
D53 --> D364
D54 --> D365
D55 --> D366
D56 --> D367
-----------------------------------------------------------------
sch/timex3_sch.pro
View file @ 0258cddf
update=03/04/2015 14:10:31
update=12/06/2015 14:12:24
last_client=eeschema
[pcbnew]
[pcbnew/libraries]
......@@ -25,11 +25,6 @@ EquName1=devcms
[eeschema]
version=1
LibDir=../../KiCad/Lib/symbols
NetFmtName=
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
[eeschema/libraries]
LibName1=capacitors/capacitors_aluminium
LibName2=capacitors/capacitors_ceramic
......
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