... | ... | @@ -40,7 +40,7 @@ core for Xilinx Spartan-6 FPGAs. |
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- Input signal.
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- Calibration signal.
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- Coarse counter reset.
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- Reset.
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- Full reset (and recalibrate).
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- Clock.
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- Output signals (without host interface module):
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- Startup calibration in progress.
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