minor and major changes from recent issues

fea68e62 · Michal Gaska · b97be185 · fea68e62 · fea68e62 · fea68e62
Commit fea68e62 authored Jul 22, 2020 by Michal Gaska
50 changed files
--- a/AFPGA_MISC.SchDoc
+++ b/AFPGA_MISC.SchDoc
--- a/PCB-Layout/EDA-xxxxx-V1-0_pcb.PcbDoc
+++ b/PCB-Layout/EDA-xxxxx-V1-0_pcb.PcbDoc
--- a/Project Logs for SVEC/AFPGA SCH ECO 22.07.2020 14-50-52.LOG
+++ b/Project Logs for SVEC/AFPGA SCH ECO 22.07.2020 14-50-52.LOG
+Change Component Designator: Old Designator=HS? New Designator=HS1
--- a/Project Logs for SVEC/EDA-02530-V3-0_pcb PCB ECO 10.06.2020 10-50-10.LOG
+++ b/Project Logs for SVEC/EDA-02530-V3-0_pcb PCB ECO 10.06.2020 10-50-10.LOG
+Removed Member From Class: ClassName=U_PowerSupplies Member=B9
+Change Component Designator: OldDesignator=C447 NewDesignator=C448
--- a/Project Logs for SVEC/EDA-xxxxx-V1-0_pcb PCB ECO 19.07.2020 12-51-58.LOG
+++ b/Project Logs for SVEC/EDA-xxxxx-V1-0_pcb PCB ECO 19.07.2020 12-51-58.LOG
+Removed Pin From Net: NetName=GND Pin=B12-1
+Removed Pin From Net: NetName=GND Pin=B13-1
+Removed Pin From Net: NetName=GND Pin=B14-1
+Removed Pin From Net: NetName=GND Pin=B15-1
+Removed Member From Class: ClassName=U_DDR3_SODIMM Member=C448
+Added Pin To Net: NetName=Chassis Pin=B12-1
+Added Pin To Net: NetName=Chassis Pin=B13-1
+Added Pin To Net: NetName=Chassis Pin=B14-1
+Added Pin To Net: NetName=Chassis Pin=B15-1
+Added Pin To Net: NetName=Chassis Pin=R102-2
+Added Pin To Net: NetName=Chassis Pin=R104-2
+Added Pin To Net: NetName=Chassis Pin=TP3-1
+Added Pin To Net: NetName=Chassis Pin=TP6-1
+Added Net: Name=Chassis
+Added Member To Class: ClassName=U_DDR3_SODIMM Member=Component C447 100nF
--- a/Project Logs for SVEC/EDA-xxxxx-V1-0_pcb PCB ECO 19.07.2020 13-48-03.LOG
+++ b/Project Logs for SVEC/EDA-xxxxx-V1-0_pcb PCB ECO 19.07.2020 13-48-03.LOG
+Removed Pin From Net: NetName=GND Pin=B12-1
+Removed Pin From Net: NetName=GND Pin=B13-1
+Removed Pin From Net: NetName=GND Pin=B14-1
+Removed Pin From Net: NetName=GND Pin=B15-1
+Removed Member From Class: ClassName=U_DDR3_SODIMM Member=C448
+Added Pin To Net: NetName=Chassis Pin=B12-1
+Added Pin To Net: NetName=Chassis Pin=B13-1
+Added Pin To Net: NetName=Chassis Pin=B14-1
+Added Pin To Net: NetName=Chassis Pin=B15-1
+Added Pin To Net: NetName=Chassis Pin=R102-2
+Added Pin To Net: NetName=Chassis Pin=R104-2
+Added Pin To Net: NetName=Chassis Pin=TP3-1
+Added Pin To Net: NetName=Chassis Pin=TP6-1
+Added Net: Name=Chassis
+Added Member To Class: ClassName=U_DDR3_SODIMM Member=Component C447 100nF
--- a/Project Logs for SVEC/EDA-xxxxx-V1-0_pcb PCB ECO 22.07.2020 14-51-53.LOG
+++ b/Project Logs for SVEC/EDA-xxxxx-V1-0_pcb PCB ECO 22.07.2020 14-51-53.LOG
+Change Component Comment : Designator=Designator7 Old Comment=Comment New Comment=Heat Sink 2 Pads
+Change Component Designator: OldDesignator=Designator7 NewDesignator=HS1
+Change component parameters: Designator = "HS1"; Footprint = "HSINK_WAKEFIELD_960-29-18-D-AB-0"; UniqueID = "\QKPLMLQB\ILCFTJRP"
+Change component parameters. Clean all parameters for all variants
+Change component parameters (AddParameter): Name = "Author"; Value = "CERN DEM BC"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "ComponentHeight"; Value = "18mm"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "Component Type"; Value = "Mechanical"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "CreateDate"; Value = "29.01.2020"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "HelpURL"; Value = "\\cern.ch\dfs\Applications\Altium\Datasheets\HSINK_WAKEFIELD_960-29-18-D-AB-0.pdf"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "LatestRevisionDate"; Value = "29.01.2020"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "Manufacturer"; Value = "WAKEFIELD-VETTE"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "Manufacturer Part Number"; Value = "960-29-18-D-AB-0"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "Mounted"; Value = "Yes"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "PackageDescription"; Value = "Extruded Heat Sink for PCB Mounting With Plastic Push Pin - L 30mm X W 29.5mm H 18mm"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "Part Description"; Value = "Extruded Heat Sink for PCB Mounting With Plastic Push Pin, Height 18mm"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "Part Number"; Value = "HSINK_WAKEFIELD_960-29-18-D-AB-0"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "Pin Count"; Value = "2"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "PressFit"; Value = "No"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "Sense"; Value = "No"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "SMD"; Value = "No"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "Socket"; Value = "No"; VariantName = "[No Variations]"
+Change component parameters (AddParameter): Name = "Status"; Value = "None"; VariantName = "[No Variations]"
+Added Class: Name=U_AFPGA
+Added Room: Name=U_AFPGA
--- a/Project Logs for SVEC/VME_buffers_address SCH ECO 10.06.2020 10-47-35.LOG
+++ b/Project Logs for SVEC/VME_buffers_address SCH ECO 10.06.2020 10-47-35.LOG
+Change Component Designator: Old Designator=C? New Designator=C448
--- a/SVEC.PrjPcb
+++ b/SVEC.PrjPcb
@@ -28,7 +28,7 @@ DItemRevisionGUID=
 ReportSuppressedErrorsInMessages=0
 FSMCodingStyle=eFMSDropDownList_OneProcess
 FSMEncodingStyle=eFMSDropDownList_OneHot
-OutputPath=Project Outputs for SVEC
+OutputPath=
 LogFolderPath=
 ManagedProjectGUID=
 IncludeDesignInRelease=0
@@ -259,7 +259,7 @@ GenerateClassCluster=0
 DocumentUniqueId=

 [Document14]
-DocumentPath=PCB-Layout\EDA-02530-V3-0_pcb.PcbDoc
+DocumentPath=PCB-Layout\EDA-xxxxx-V1-0_pcb.PcbDoc
 AnnotationEnabled=1
 AnnotateStartValue=1
 AnnotationIndexControlEnabled=0
@@ -561,7 +561,7 @@ SCH_ShowNote=-1
 SCH_ShowNoteCollapsed=-1

 [Generic_EDE]
-OutputDir=Project Outputs for SVEC
+OutputDir=

 [OutputGroup1]
 Name=Netlist Outputs

--- a/Schematics/AFPGA.SchDoc
+++ b/Schematics/AFPGA.SchDoc
--- a/Schematics/AFPGA_1V0.SchDoc
+++ b/Schematics/AFPGA_1V0.SchDoc
--- a/Schematics/AFPGA_FMC1_FMC2.SchDoc
+++ b/Schematics/AFPGA_FMC1_FMC2.SchDoc
--- a/Schematics/AFPGA_power.SchDoc
+++ b/Schematics/AFPGA_power.SchDoc
--- a/Schematics/CERN-A3.SchDot
+++ b/Schematics/CERN-A3.SchDot
--- a/Schematics/Clk_generation.SchDoc
+++ b/Schematics/Clk_generation.SchDoc
--- a/Schematics/DDR3_SODIMM.SchDoc
+++ b/Schematics/DDR3_SODIMM.SchDoc
--- a/Schematics/FMC_CONNECTORS.SchDoc
+++ b/Schematics/FMC_CONNECTORS.SchDoc
--- a/Schematics/FPGA_GTP.SchDoc
+++ b/Schematics/FPGA_GTP.SchDoc
--- a/Schematics/Front_panel.SchDoc
+++ b/Schematics/Front_panel.SchDoc
--- a/Schematics/JTAG Chain + SFPGA Flash.SchDoc
+++ b/Schematics/JTAG Chain + SFPGA Flash.SchDoc
--- a/Schematics/Power_supplies.SchDoc
+++ b/Schematics/Power_supplies.SchDoc
--- a/Schematics/SFPGA.SchDoc
+++ b/Schematics/SFPGA.SchDoc
--- a/Schematics/SFPGA_power.SchDoc
+++ b/Schematics/SFPGA_power.SchDoc
--- a/Schematics/SVEC_TOP.SchDoc
+++ b/Schematics/SVEC_TOP.SchDoc
--- a/Schematics/Slow_IO_MUX.SchDoc
+++ b/Schematics/Slow_IO_MUX.SchDoc
--- a/Schematics/USB_interface.SchDoc
+++ b/Schematics/USB_interface.SchDoc
--- a/Schematics/VME_buffers.SchDoc
+++ b/Schematics/VME_buffers.SchDoc
--- a/Schematics/VME_buffers_address.SchDoc
+++ b/Schematics/VME_buffers_address.SchDoc
--- a/Schematics/VME_buffers_data.SchDoc
+++ b/Schematics/VME_buffers_data.SchDoc
--- a/Schematics/VME_connectors.SchDoc
+++ b/Schematics/VME_connectors.SchDoc
--- a/Schematics/__Previews/AFPGA.SchDocPreview
+++ b/Schematics/__Previews/AFPGA.SchDocPreview
--- a/Schematics/__Previews/AFPGA_1V0.SchDocPreview
+++ b/Schematics/__Previews/AFPGA_1V0.SchDocPreview
--- a/Schematics/__Previews/AFPGA_FMC1_FMC2.SchDocPreview
+++ b/Schematics/__Previews/AFPGA_FMC1_FMC2.SchDocPreview
--- a/Schematics/__Previews/AFPGA_power.SchDocPreview
+++ b/Schematics/__Previews/AFPGA_power.SchDocPreview
--- a/Schematics/__Previews/Clk_generation.SchDocPreview
+++ b/Schematics/__Previews/Clk_generation.SchDocPreview
--- a/Schematics/__Previews/DDR3_SODIMM.SchDocPreview
+++ b/Schematics/__Previews/DDR3_SODIMM.SchDocPreview
--- a/Schematics/__Previews/FMC_connectors.SchDocPreview
+++ b/Schematics/__Previews/FMC_connectors.SchDocPreview
--- a/Schematics/__Previews/FPGA_GTP.SchDocPreview
+++ b/Schematics/__Previews/FPGA_GTP.SchDocPreview
--- a/Schematics/__Previews/Front_panel.SchDocPreview
+++ b/Schematics/__Previews/Front_panel.SchDocPreview
--- a/Schematics/__Previews/JTAG chain + SFPGA flash.SchDocPreview
+++ b/Schematics/__Previews/JTAG chain + SFPGA flash.SchDocPreview
--- a/Schematics/__Previews/Power_supplies.SchDocPreview
+++ b/Schematics/__Previews/Power_supplies.SchDocPreview
--- a/Schematics/__Previews/SFPGA.SchDocPreview
+++ b/Schematics/__Previews/SFPGA.SchDocPreview
--- a/Schematics/__Previews/SFPGA_power.SchDocPreview
+++ b/Schematics/__Previews/SFPGA_power.SchDocPreview
--- a/Schematics/__Previews/SVEC_top.SchDocPreview
+++ b/Schematics/__Previews/SVEC_top.SchDocPreview
--- a/Schematics/__Previews/Slow_IO_MUX.SchDocPreview
+++ b/Schematics/__Previews/Slow_IO_MUX.SchDocPreview
--- a/Schematics/__Previews/USB_interface.SchDocPreview
+++ b/Schematics/__Previews/USB_interface.SchDocPreview
--- a/Schematics/__Previews/VME_buffers.SchDocPreview
+++ b/Schematics/__Previews/VME_buffers.SchDocPreview
--- a/Schematics/__Previews/VME_buffers_address.SchDocPreview
+++ b/Schematics/__Previews/VME_buffers_address.SchDocPreview
--- a/Schematics/__Previews/VME_buffers_data.SchDocPreview
+++ b/Schematics/__Previews/VME_buffers_data.SchDocPreview
--- a/Schematics/__Previews/VME_connectors.SchDocPreview
+++ b/Schematics/__Previews/VME_connectors.SchDocPreview